Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[platform/kernel/u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index a3b5c7c..8382e3c 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -17,7 +17,6 @@
 #define CONFIG_MPC86xx         1       /* MPC86xx */
 #define CONFIG_MPC8610         1       /* MPC8610 specific */
 #define CONFIG_MPC8610HPCD     1       /* MPC8610HPCD board specific */
-#define CONFIG_NUM_CPUS                1       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC 0x100   /* Reset vector used by Linux */
 
 #define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
@@ -81,6 +80,7 @@
 
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
+#define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
@@ -102,8 +102,6 @@
 #define CONFIG_SYS_MAX_DDR_BAT_SIZE    0x80000000      /* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
-#define MPC86xx_DDR_SDRAM_CLK_CNTL
-
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -179,7 +177,7 @@
 #define PIXIS_VSPEED1          0x18    /* VELA VSpeed 1 */
 #define PIXIS_VCLKH            0x19    /* VELA VCLKH register */
 #define PIXIS_VCLKL            0x1A    /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK    0x0C    /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK    0xC0    /* Reset altbank mask */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     2               /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
@@ -253,9 +251,6 @@
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE  8192
 
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -346,10 +341,8 @@
  * BAT0                2G      Cacheable, non-guarded
  * 0x0000_0000 2G      DDR
  */
-#define CONFIG_SYS_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U      CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_DBAT0L      (BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L      (BATL_PP_RW)
 
 /*
  * BAT1                1G      Cache-inhibited, guarded