Merge branch 'master' of /home/wd/git/u-boot/custodians

[platform/kernel/u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 27517e5..7619328 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -17,7 +17,6 @@
 #define CONFIG_MPC86xx         1       /* MPC86xx */
 #define CONFIG_MPC8610         1       /* MPC8610 specific */
 #define CONFIG_MPC8610HPCD     1       /* MPC8610HPCD board specific */
-#define CONFIG_NUM_CPUS                1       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC 0x100   /* Reset vector used by Linux */
 
 #define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
@@ -34,8 +33,6 @@
 #define CONFIG_SYS_DIAG_ADDR           0xff800000
 #endif
 
-#define CONFIG_SYS_RESET_ADDRESS       0xfff00100
-
 /*
  * virtual address to be used for temporary mappings.  There
  * should be 128k free at this VA.
@@ -83,6 +80,7 @@
 
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
+#define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 #define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
 #define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
@@ -273,30 +271,28 @@
  * General PCI
  * Addresses are mapped 1-1.
  */
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_BUS                0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BUS
+#define CONFIG_SYS_PCI1_MEM_VIRT       CONFIG_SYS_PCI1_MEM_BUS
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x10000000      /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe1000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe1000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
-/* For RTL8139 */
-#define KSEG1ADDR(x)   ({u32 _x = le32_to_cpu(*(u32 *)(x)); (&_x); })
-#define _IO_BASE               0x00000000
-
 /* controller 1, Base address 0xa000 */
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BUS
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_BUS                0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /* 1M */
 
 /* controller 2, Base Address 0x9000 */
-#define CONFIG_SYS_PCIE2_MEM_BASE      0x90000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BASE
+#define CONFIG_SYS_PCIE2_MEM_BUS       0x90000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      CONFIG_SYS_PCIE2_MEM_BUS
 #define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000      /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000      /* reuse mem LAW */
+#define CONFIG_SYS_PCIE2_IO_BUS                0x00000000      /* reuse mem LAW */
 #define CONFIG_SYS_PCIE2_IO_PHYS       0xe2000000
 #define CONFIG_SYS_PCIE2_IO_SIZE       0x00100000      /* 1M */
 
@@ -321,7 +317,7 @@
 #define CONFIG_PCI_OHCI                1
 #define CONFIG_USB_OHCI_NEW            1
 #define CONFIG_USB_KEYBOARD    1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_SYS_USB_EVENT_POLL      1
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME  "ohci_pci"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
@@ -364,7 +360,7 @@
 
 #define CONFIG_SYS_DBAT1L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
                        | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT1U      (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_1G | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT1U      (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT1L      (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT1U      CONFIG_SYS_DBAT1U
 
@@ -375,7 +371,7 @@
 
 #define CONFIG_SYS_DBAT2L      (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
                        | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2U      (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
 #define CONFIG_SYS_IBAT2L      (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CONFIG_SYS_IBAT2U      CONFIG_SYS_DBAT2U
 
@@ -489,7 +485,7 @@
 #define CONFIG_CMD_MII
 
 #if defined(CONFIG_SYS_RAMBOOT)
-#undef CONFIG_CMD_ENV
+#undef CONFIG_CMD_SAVEENV
 #endif
 
 #if defined(CONFIG_PCI)