ppc4xx: Big header cleanup part 2, mostly PPC405 related

[platform/kernel/u-boot.git] / include / configs / MPC8610HPCD.h

diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h
index 2f40ef4..58d3d99 100644 (file)
--- a/include/configs/MPC8610HPCD.h
+++ b/include/configs/MPC8610HPCD.h
@@ -17,7 +17,6 @@
 #define CONFIG_MPC86xx         1       /* MPC86xx */
 #define CONFIG_MPC8610         1       /* MPC8610 specific */
 #define CONFIG_MPC8610HPCD     1       /* MPC8610HPCD board specific */
-#define CONFIG_NUM_CPUS                1       /* Number of CPUs in the system */
 #define CONFIG_LINUX_RESET_VEC 0x100   /* Reset vector used by Linux */
 
 #define CONFIG_FSL_DIU_FB      1       /* FSL DIU */
@@ -25,9 +24,12 @@
 /* video */
 #undef CONFIG_VIDEO
 
-#if defined(CONFIG_VIDEO)
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
 #define CONFIG_CFB_CONSOLE
 #define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_BMP_LOGO
 #endif
 
 #ifdef RUN_DIAG
@@ -81,10 +83,7 @@
 
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH   0x0
-
-#define CONFIG_SYS_PCI1_ADDR           (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCIE1_ADDR          (CONFIG_SYS_CCSRBAR+0xa000)
-#define CONFIG_SYS_PCIE2_ADDR          (CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_CCSRBAR_PHYS                CONFIG_SYS_CCSRBAR_PHYS_LOW
 
 #define CONFIG_SYS_DIU_ADDR            (CONFIG_SYS_CCSRBAR+0x2c000)
 
@@ -102,8 +101,6 @@
 #define CONFIG_SYS_MAX_DDR_BAT_SIZE    0x80000000      /* BAT mapping size */
 #define CONFIG_VERY_BIG_RAM
 
-#define MPC86xx_DDR_SDRAM_CLK_CNTL
-
 #define CONFIG_NUM_DDR_CONTROLLERS     1
 #define CONFIG_DIMM_SLOTS_PER_CTLR     1
 #define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
@@ -179,7 +176,7 @@
 #define PIXIS_VSPEED1          0x18    /* VELA VSpeed 1 */
 #define PIXIS_VCLKH            0x19    /* VELA VCLKH register */
 #define PIXIS_VCLKL            0x1A    /* VELA VCLKL register */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK    0x0C    /* Reset altbank mask*/
+#define CONFIG_SYS_PIXIS_VBOOT_MASK    0xC0    /* Reset altbank mask */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     2               /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      1024            /* sectors per device */
@@ -253,9 +250,6 @@
 /* maximum size of the flat tree (8K) */
 #define OF_FLAT_TREE_MAX_SIZE  8192
 
-#define CONFIG_SYS_64BIT_VSPRINTF      1
-#define CONFIG_SYS_64BIT_STRTOUL       1
-
 /*
  * I2C
  */
@@ -317,7 +311,7 @@
 #define CONFIG_PCI_OHCI                1
 #define CONFIG_USB_OHCI_NEW            1
 #define CONFIG_USB_KEYBOARD    1
-#define CONFIG_SYS_DEVICE_DEREGISTER
+#define CONFIG_SYS_STDIO_DEREGISTER
 #define CONFIG_SYS_USB_EVENT_POLL      1
 #define CONFIG_SYS_USB_OHCI_SLOT_NAME  "ohci_pci"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
@@ -346,10 +340,8 @@
  * BAT0                2G      Cacheable, non-guarded
  * 0x0000_0000 2G      DDR
  */
-#define CONFIG_SYS_DBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_DBAT0U      (BATU_BL_2G | BATU_VS | BATU_VP)
-#define CONFIG_SYS_IBAT0L      (BATL_PP_RW | BATL_MEMCOHERENCE )
-#define CONFIG_SYS_IBAT0U      CONFIG_SYS_DBAT0U
+#define CONFIG_SYS_DBAT0L      (BATL_PP_RW)
+#define CONFIG_SYS_IBAT0L      (BATL_PP_RW)
 
 /*
  * BAT1                1G      Cache-inhibited, guarded