/*
* MPC8610HPCD board configuration file
- *
*/
#ifndef __CONFIG_H
#define CONFIG_NUM_CPUS 1 /* Number of CPUs in the system */
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
+#define CONFIG_FSL_DIU_FB 1 /* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
#ifdef RUN_DIAG
#define CFG_DIAG_ADDR 0xff800000
#endif
#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */
#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
-#undef CONFIG_DDR_DLL /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
-#define CONFIG_DDR_ECC /* only for ECC DDR module */
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
+#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */
#define CONFIG_ALTIVEC 1
/*
*/
#define CFG_L2
#define L2_INIT 0
-#define L2_ENABLE (L2CR_L2E)
+#define L2_ENABLE (L2CR_L2E |0x00100000 )
#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
#endif
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_MISC_INIT_R 1
-#undef CFG_DRAM_TEST /* memory test, takes time */
#define CFG_MEMTEST_START 0x00200000 /* memtest region */
#define CFG_MEMTEST_END 0x00400000
-#define CFG_ALT_MEMTEST
/*
* Base addresses -- Note these are effective addresses where the
#define CFG_DIU_ADDR (CFG_CCSRBAR+0x2c000)
-/*
- * DDR Setup
- */
+/* DDR Setup */
+#define CONFIG_FSL_DDR2
+#undef CONFIG_FSL_DDR_INTERACTIVE
+#define CONFIG_SPD_EEPROM /* Use SPD for DDR */
+#define CONFIG_DDR_SPD
+
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#define MPC86xx_DDR_SDRAM_CLK_CNTL
-#if defined(CONFIG_SPD_EEPROM)
-/*
- * Determine DDR configuration from I2C interface.
- */
-#define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */
-#else
-/*
- * Manually set up DDR1 parameters
- */
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 1
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */
+/* These are used when DDR doesn't use SPD. */
#define CFG_SDRAM_SIZE 256 /* DDR is 256MB */
#if 0 /* TODO */
#define CFG_DDR_CS0_BNDS 0x0000000F
#define CFG_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
-#define CFG_DDR_EXT_REFRESH 0x00000000
+#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 0x00260802
#define CFG_DDR_TIMING_1 0x3935d322
#define CFG_DDR_TIMING_2 0x14904cc8
#define CFG_DDR_ERR_INT_EN 0x00000000
#define CFG_DDR_ERR_DIS 0x00000000
#define CFG_DDR_SBE 0x000f0000
- /* Not used in fixed_sdram function */
+
+/*
+ * FIXME: Not used in fixed_sdram function
+ */
#define CFG_DDR_MODE 0x00000022
#define CFG_DDR_CS1_BNDS 0x00000000
#define CFG_DDR_CS2_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS4_BNDS 0x00000FFF /* Not done */
#define CFG_DDR_CS5_BNDS 0x00000FFF /* Not done */
#endif
-#endif
-#define CFG_ID_EEPROM
-#define ID_EEPROM_ADDR 0x57
+
+#define CONFIG_ID_EEPROM
+#define CFG_I2C_EEPROM_NXID
+#define CONFIG_ID_EEPROM
+#define CFG_I2C_EEPROM_ADDR 0x57
+#define CFG_I2C_EEPROM_ADDR_LEN 1
#define CFG_FLASH_BASE 0xf0000000 /* start of FLASH 128M */
#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
+#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xe8000000 /* PIXIS registers */
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
#define PIXIS_VER 0x1 /* Board version at offset 1 */
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
+#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/
#define PIXIS_VCTL 0x10 /* VELA Control Register */
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
+#define CFG_PIXIS_VBOOT_MASK 0x0C /* Reset altbank mask*/
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_EMPTY_INFO
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
-#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 1
/*
* Pass open firmware flat tree to kernel
*/
-#define CONFIG_OF_FLAT_TREE 1
-#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_OF_BOARD_SETUP 1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
+
/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE 8192
-#define OF_CPU "PowerPC,8610@0"
-#define OF_SOC "soc@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc@e0000000/serial@4500"
-
#define CFG_64BIT_VSPRINTF 1
#define CFG_64BIT_STRTOUL 1
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CONFIG_NET_MULTI
+#define CONFIG_CMD_NET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
+#define CONFIG_CMD_REGINFO
-#if 0 /* TODO */
-/* enable onboard uli network support */
+#define CONFIG_ULI526X
+#ifdef CONFIG_ULI526X
+#define CONFIG_ETHADDR 00:E0:0C:00:00:01
#endif
-#define CONFIG_RTL8139
-#define CONFIG_SK98
-#define CONFIG_EEPRO100
-#define CONFIG_TULIP
-
-#if 0 /* TODO */
/************************************************************
* USB support
************************************************************/
-#define CONFIG_USB_OHCI 1
+#define CONFIG_PCI_OHCI 1
+#define CONFIG_USB_OHCI_NEW 1
#define CONFIG_USB_KEYBOARD 1
#define CFG_DEVICE_DEREGISTER
-#define CFG_USB_INTERRUPT_POLL 1
-#endif
+#define CFG_USB_EVENT_POLL 1
+#define CFG_USB_OHCI_SLOT_NAME "ohci_pci"
+#define CFG_USB_OHCI_MAX_ROOT_PORTS 15
+#define CFG_OHCI_SWAP_REG_ACCESS 1
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000
#define CFG_IBAT1U CFG_DBAT1U
/*
- * BAT2 32M Cache-inhibited, guarded
+ * BAT2 16M Cache-inhibited, guarded
* 0xe100_0000 1M PCI-1 I/O
- * 0xe200_0000 1M PCI-Express 2 I/O
- *
*/
#define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
/*
- * BAT3 1M Cache-inhibited, guarded
+ * BAT3 32M Cache-inhibited, guarded
+ * 0xe200_0000 1M PCI-Express 2 I/O
* 0xe300_0000 1M PCI-Express 1 I/O
- *
*/
-#define CFG_DBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
+#define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
-#define CFG_DBAT3U (CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP)
-#define CFG_IBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
+#define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U CFG_DBAT3U
/*
* Environment
*/
#ifndef CFG_RAMBOOT
-#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
-#define CFG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
-#define CFG_ENV_SIZE 0x2000
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */
+#define CONFIG_ENV_SIZE 0x2000
#else
-#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
-#define CFG_ENV_SIZE 0x2000
+#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
+#define CONFIG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
+#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SCSI
#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_USB
#endif
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_WATCHDOG /* watchdog enabled */
+#define CFG_WATCHDOG_FREQ 5000 /* Feed interval, 5s */
+
+/*DIU Configuration*/
+#define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 32768
-#define CFG_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-#endif
-
/*
* Internal Definitions
*
"dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
"mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
-
+#ifdef ENV_DEBUG
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "dtbaddr=c00000\0" \
- "dtbfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
"bdev=sda3\0" \
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
"diuregs=md e002c000 1d\0" \
"dium=mw e002c01c\0" \
"diuerr=md e002c014 1\0" \
- "othbootargs=debug\0" \
+ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 debug\0" \
+ "monitor=0-DVI\0" \
"pmregs=md e00e1000 2b\0" \
"lawregs=md e0000c08 4b\0" \
"lbcregs=md e0005000 36\0" \
PCI_ENV \
PCIE_ENV \
DMA_ENV
+#else
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+ "bdev=sda3\0" \
+ "othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0\0"\
+ "monitor=0-DVI\0"
+#endif
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr $ramdiskaddr $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
#define CONFIG_BOOTCOMMAND \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
- "tftp $dtbaddr $dtbfile;" \
- "bootm $loadaddr - $dtbaddr"
+ "tftp $fdtaddr $fdtfile;" \
+ "bootm $loadaddr - $fdtaddr"
#endif /* __CONFIG_H */
projects / platform / kernel / u-boot.git / blobdiff