+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#include "../board/freescale/common/ics307_clk.h"
+#include <linux/stringify.h>
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xeff40000
-#endif
+#include "../board/freescale/common/ics307_clk.h"
#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
#endif
/* High Level Configuration Options */
-#define CONFIG_MP 1 /* support multiple processors */
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
#define CONFIG_ENABLE_36BIT_PHYS 1
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_ADDR_MAP 1
-#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x7fffffff
-
/*
* Config the L2 Cache as L2 SRAM
*/
/* DDR Setup */
#define CONFIG_VERY_BIG_RAM
-#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#error ("CONFIG_SPD_EEPROM is required")
#endif
-#undef CONFIG_CLOCKS_IN_MHZ
-
/*
* Memory map
*
#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
-#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
-
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
* open - index 2
* shorted - index 1
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
#endif
-#undef CONFIG_EEPRO100
-#undef CONFIG_TULIP
#ifndef CONFIG_PCI_PNP
#define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
#endif /* SCSI */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
* Environment
*/
-#if defined(CONFIG_SYS_RAMBOOT)
-
-#else
- #if CONFIG_SYS_MONITOR_BASE > 0xfff80000
- #define CONFIG_ENV_ADDR 0xfff80000
- #else
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #endif
- #define CONFIG_ENV_SIZE 0x2000
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
-#endif
-
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
/*
#define CONFIG_IPADDR 192.168.1.254
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */