*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
/* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#undef CONFIG_DDR_DLL
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */
/* These are used when DDR doesn't use SPD. */
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
-#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
-#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
-#define CONFIG_SYS_DDR_TIMING_3 0x00000000
-#define CONFIG_SYS_DDR_TIMING_0 0x00260802
-#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
-#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
-#define CONFIG_SYS_DDR_MODE_1 0x00480432
+#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */
+#define CONFIG_SYS_DDR_TIMING_3 0x00020000
+#define CONFIG_SYS_DDR_TIMING_0 0x00260802
+#define CONFIG_SYS_DDR_TIMING_1 0x626b2634
+#define CONFIG_SYS_DDR_TIMING_2 0x062874cf
+#define CONFIG_SYS_DDR_MODE_1 0x00440462
#define CONFIG_SYS_DDR_MODE_2 0x00000000
-#define CONFIG_SYS_DDR_INTERVAL 0x06180100
+#define CONFIG_SYS_DDR_INTERVAL 0x0c300100
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
-#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
-#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
+#define CONFIG_SYS_DDR_CLK_CTRL 0x00800000
+#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
-#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
-#define CONFIG_SYS_DDR_CONTROL2 0x04400010
+#define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */
+#define CONFIG_SYS_DDR_CONTROL2 0x24400000
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
* Localbus non-cacheable
* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
+ * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
| PIXIS_VCFGEN1_TSEC3SER \
| PIXIS_VCFGEN1_TSEC4SER)
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_NAND_BASE 0xffa00000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
+ CONFIG_SYS_NAND_BASE + 0x40000, \
+ CONFIG_SYS_NAND_BASE + 0x80000,\
+ CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE 4
+#define NAND_MAX_CHIPS 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_PGS /* Large Page*/ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+
/* Serial Port - controlled on board with jumper J8
* open - index 2
* shorted - index 1
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
projects / platform / kernel / u-boot.git / blobdiff