+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2009-2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#define CONFIG_PCIE1 1 /* PCIE controller */
#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_QE /* Enable QE */
#define CONFIG_ENV_OVERWRITE
#ifndef __ASSEMBLY__
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
-#define CONFIG_BOARD_EARLY_INIT_R 1
#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#endif
/* DDR Setup */
-#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Chip select 3 - NAND */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/* QE microcode/firmware address */
-#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_QE_FW_ADDR 0xfff00000
/*
#undef CONFIG_WATCHDOG /* watchdog disabled */
#ifdef CONFIG_MMC
-#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif
/*
* Environment Configuration
*/
-#define CONFIG_HOSTNAME mpc8569mds
+#define CONFIG_HOSTNAME "mpc8569mds"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "your.uImage"