/*
- * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ * Copyright (C) 2009 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the MDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_ENABLE_36BIT_PHYS 1
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
+#define CONFIG_HWCONFIG
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+/* Chip select 3 - NAND */
+#define CONFIG_SYS_NAND_BASE 0xFC000000
+#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V) /* valid */
+#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+ | OR_FCM_CSCT \
+ | OR_FCM_CST \
+ | OR_FCM_CHT \
+ | OR_FCM_SCY_1 \
+ | OR_FCM_TRLX \
+ | OR_FCM_EHTR)
+#define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
/*
* SDRAM on the LocalBus
/* Serial Port */
#define CONFIG_CONS_INDEX 1
+#define CONFIG_SERIAL_MULTI 1
#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
#define PLPPAR1_I2C_BIT_MASK 0x0000000F
#define PLPPAR1_I2C2_VAL 0x00000000
+#define PLPPAR1_ESDHC_VAL 0x0000000A
#define PLPDIR1_I2C_BIT_MASK 0x0000000F
#define PLPDIR1_I2C2_VAL 0x0000000F
+#define PLPDIR1_ESDHC_VAL 0x00000006
/*
* General PCI
/*
* QE UEC ethernet configuration
*/
+#define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */
+#undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */
#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
#define CONFIG_UEC_ETH
#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC1_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR 7
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH1 */
#define CONFIG_UEC_ETH2 /* GETH2 */
#define CONFIG_HAS_ETH1
#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC2_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR 1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
#define CONFIG_UEC_ETH3 /* GETH3 */
#define CONFIG_HAS_ETH2
#ifdef CONFIG_UEC_ETH3
#define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */
#define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC3_TX_CLK QE_CLK12
#define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC3_PHY_ADDR 2
#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
#define CONFIG_UEC_ETH4 /* GETH4 */
#define CONFIG_HAS_ETH3
#ifdef CONFIG_UEC_ETH4
#define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */
#define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
#define CONFIG_SYS_UEC4_TX_CLK QE_CLK17
#define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH
#define CONFIG_SYS_UEC4_PHY_ADDR 3
#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6 /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR 4
+#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8 /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR 6
+#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH8 */
+
#endif /* CONFIG_QE */
#if defined(CONFIG_PCI)
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
/* Initial Memory map for Linux*/
/*
projects / platform / kernel / u-boot.git / blobdiff