powerpc: mpc85xx: Move CONFIG_FSL_PCIE_RESET to Kconfig

[platform/kernel/u-boot.git] / include / configs / MPC8548CDS.h

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index c85ad5d..b37601c 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -20,7 +20,6 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
 #define CONFIG_PCI_INDIRECT_BRIDGE 1   /* indirect PCI bridge support */
-#define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 
 #define CONFIG_ENV_OVERWRITE
@@ -56,7 +55,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR
 
 /* DDR Setup */
-#undef CONFIG_FSL_DDR_INTERACTIVE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 
@@ -169,8 +167,6 @@ extern unsigned long get_clock_freq(void);
 
 #define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
 #define CONFIG_HWCONFIG                        /* enable hwconfig */
@@ -396,7 +392,6 @@ extern unsigned long get_clock_freq(void);
 
 #if defined(CONFIG_TSEC_ENET)
 
-#define CONFIG_MII             1       /* MII PHY management */
 #define CONFIG_TSEC1   1
 #define CONFIG_TSEC1_NAME      "eTSEC0"
 #define CONFIG_TSEC2   1
@@ -407,8 +402,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC4_NAME      "eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
-#define CONFIG_PHY_MARVELL
-
 #define TSEC1_PHY_ADDR         0
 #define TSEC2_PHY_ADDR         1
 #define TSEC3_PHY_ADDR         2