+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_36BIT
-#define CONFIG_PHYS_64BIT
-#endif
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
-#define CONFIG_MPC8548 1 /* MPC8548 specific */
-#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-#endif
-
#define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */
-#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
-#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#undef CONFIG_PCI2
-#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
-#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_VIA
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
-#define CONFIG_FSL_DDR2
-#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
*
*/
-
/*
* Local Bus Definitions
*/
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_HWCONFIG /* enable hwconfig */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
/*
* I2C
*/
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED 400000
+#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
+#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
#endif
-#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
/*
#endif
#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
-#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE 1
+#define CONFIG_SYS_PCIE1_NAME "Slot"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
-
#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
-#define CONFIG_PHY_MARVELL
-
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
/* Options are: eTSEC[0-3] */
#define CONFIG_ETHPRIME "eTSEC0"
-#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/
-#define CONFIG_ENV_IS_IN_FLASH 1
-#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
-#define CONFIG_ENV_ADDR 0xfff80000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#endif
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
-#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SETEXPR
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/*
* For booting Linux, the board info and command line data
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
/*
* Environment Configuration
*/
-
-/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
#define CONFIG_HAS_ETH2
-#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
#define CONFIG_HAS_ETH3
-#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
#endif
#define CONFIG_IPADDR 192.168.1.253
-#define CONFIG_HOSTNAME unknown
+#define CONFIG_HOSTNAME "unknown"
#define CONFIG_ROOTPATH "/nfsroot"
#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
-#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
-
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
+ "fdtaddr=1e00000\0" \
"fdtfile=mpc8548cds.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
-
#define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \
projects / platform / kernel / u-boot.git / blobdiff