/*
- * Copyright 2004, 2007 Freescale Semiconductor.
+ * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
*
* See file CREDITS for list of people who contributed to this
* project.
#ifndef __CONFIG_H
#define __CONFIG_H
+#ifdef CONFIG_36BIT
+#define CONFIG_PHYS_64BIT
+#endif
+
/* High Level Configuration Options */
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC8548 1 /* MPC8548 specific */
#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE 0xfff80000
+#endif
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1 /* SRIO port 1 */
+
#define CONFIG_PCI /* enable any pci type devices */
#define CONFIG_PCI1 /* PCI controller 1 */
#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
-#undef CONFIG_RIO
#undef CONFIG_PCI2
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_VIA
-/*
- * When initializing flash, if we cannot find the manufacturer ID,
- * assume this is the AMD flash associated with the CDS board.
- * This allows booting from a promjet.
- */
-#define CONFIG_ASSUME_AMD_FLASH
-
#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
/*
* Only possible on E500 Version 2 or newer cores.
*/
#define CONFIG_ENABLE_36BIT_PHYS 1
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
+#endif
+
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
-#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
-#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
+#define CONFIG_SYS_CCSRBAR 0xe0000000
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
/* DDR Setup */
#define CONFIG_FSL_DDR2
#undef CONFIG_FSL_DDR_INTERACTIVE
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
+#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
#endif
#undef CONFIG_CLOCKS_IN_MHZ
+/*
+ * Physical Address Map
+ *
+ * 32bit:
+ * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
+ * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
+ * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
+ * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
+ * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
+ * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
+ * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
+ * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable
+ * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable
+ * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
+ * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
+ *
+ * 36bit:
+ * 0x00000_0000 0x07fff_ffff DDR 2G cacheable
+ * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable
+ * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable
+ * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable
+ * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable
+ * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable
+ * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable
+ * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable
+ * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable
+ * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable
+ * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable
+ *
+ */
+
/*
* Local Bus Definitions
* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
*/
-#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
+#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
+#endif
-#define CONFIG_SYS_BR0_PRELIM 0xff801001
-#define CONFIG_SYS_BR1_PRELIM 0xff001001
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR1_PRELIM 0xff806e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_FLASH_BANKS_LIST \
+ {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_HWCONFIG /* enable hwconfig */
/*
* SDRAM on the Local Bus
*/
-#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
-#define CONFIG_SYS_LBC_CACHE_SIZE 64
-#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
-#define CONFIG_SYS_LBC_NONCACHE_SIZE 64
-
-#define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
+#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull
+#else
+#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE
+#endif
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
/*
* FIXME: the top 17 bits of BR2.
*/
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861
+#define CONFIG_SYS_BR2_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+ | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
- * LSDMR masks
- */
-#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
-#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
-#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
-#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
-#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
-#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
-
-#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
-#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
-
-/*
* Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too.
*/
-#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \
- | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \
- | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \
- | CONFIG_SYS_LBC_LSDMR_BL8 \
- | CONFIG_SYS_LBC_LSDMR_WRC4 \
- | CONFIG_SYS_LBC_LSDMR_CL3 \
- | CONFIG_SYS_LBC_LSDMR_RFEN \
+#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
+ | LSDMR_PRETOACT7 \
+ | LSDMR_ACTTORW7 \
+ | LSDMR_BL8 \
+ | LSDMR_WRC4 \
+ | LSDMR_CL3 \
+ | LSDMR_RFEN \
)
/*
#define CONFIG_FSL_CADMUS
#define CADMUS_BASE_ADDR 0xf8000000
-#define CONFIG_SYS_BR3_PRELIM 0xf8000801
+#ifdef CONFIG_PHYS_64BIT
+#define CADMUS_BASE_ADDR_PHYS 0xff8000000ull
+#else
+#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
+#endif
+#define CONFIG_SYS_BR3_PRELIM \
+ (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
-
-#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/* Serial Port */
#define CONFIG_CONS_INDEX 2
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-#define CONFIG_SYS_64BIT_VSPRINTF 1
-#define CONFIG_SYS_64BIT_STRTOUL 1
-
/*
* I2C
*/
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
-#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
+#else
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
+#endif
#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#else
#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
-#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
-#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
-#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
#endif
+#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1
+#define CONFIG_SYS_PCIE1_NAME "Slot"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull
+#else
#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
+#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull
+#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
+#endif
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
#endif
-#ifdef CONFIG_RIO
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
-#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
-#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#if defined(CONFIG_PCI)
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#undef CONFIG_EEPRO100
#undef CONFIG_TULIP
+#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
-#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
+#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
-
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
+#define CONFIG_PHY_MARVELL
+
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
* Environment
*/
#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR 0xfff80000
+#else
+#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_CMD_ELF
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_SETEXPR
+#define CONFIG_CMD_REGINFO
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_CMDLINE_EDITING /* Command-line editing */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#if defined(CONFIG_CMD_KGDB)
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 64 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
+#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
#define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME unknown
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE 8548cds/uImage.uboot
+#define CONFIG_ROOTPATH "/nfsroot"
+#define CONFIG_BOOTFILE "8548cds/uImage.uboot"
#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_BAUDRATE 115200
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS1\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=mpc8548cds.dtb\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "hwconfig=fsl_ddr:ecc=off\0" \
+ "netdev=eth0\0" \
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "consoledev=ttyS1\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=mpc8548cds.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \