Merge branch 'cleanups' into next

[platform/kernel/u-boot.git] / include / configs / MPC8548CDS.h

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index dd447d3..95bce95 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -43,6 +43,7 @@
 #undef CONFIG_PCI2
 #define CONFIG_FSL_PCI_INIT    1       /* Use common FSL init code */
 #define CONFIG_FSL_PCIE_RESET  1       /* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT   1       /* enable 64-bit PCI resources */
 
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
@@ -68,7 +69,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CONFIG_L2_CACHE                        /* toggle L2 cache */
 #define CONFIG_BTB                     /* toggle branch predition */
-#define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
 #define CONFIG_CLEAR_LAW0              /* Clear LAW0 in cpu_init_r */
 
 /*
@@ -99,7 +99,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_DDR_SPD
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
 
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER       /* DDR controller or DMA? */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE  0xDeadBeef
 
 #define CONFIG_SYS_DDR_SDRAM_BASE      0x00000000      /* DDR is system memory*/
@@ -302,7 +302,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_BR3_PRELIM   0xf8000801
 #define CONFIG_SYS_OR3_PRELIM   0xfff00ff7
 
-#define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK       1
 #define CONFIG_SYS_INIT_RAM_ADDR       0xe4010000      /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_END        0x4000          /* End of used area in RAM */
@@ -366,29 +365,36 @@ extern unsigned long get_clock_freq(void);
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
+#define CONFIG_SYS_PCI_VIRT            0x80000000      /* 1G PCI TLB */
 #define CONFIG_SYS_PCI_PHYS            0x80000000      /* 1G PCI TLB */
 
-#define CONFIG_SYS_PCI1_MEM_BASE       0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS       CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_VIRT       0x80000000
+#define CONFIG_SYS_PCI1_MEM_BUS        0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS       0x80000000
 #define CONFIG_SYS_PCI1_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI1_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI1_IO_VIRT        0xe2000000
+#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI1_IO_PHYS        0xe2000000
 #define CONFIG_SYS_PCI1_IO_SIZE        0x00100000      /* 1M */
 
 #ifdef CONFIG_PCI2
-#define CONFIG_SYS_PCI2_MEM_BASE       0xa0000000
-#define CONFIG_SYS_PCI2_MEM_PHYS       CONFIG_SYS_PCI2_MEM_BASE
+#define CONFIG_SYS_PCI2_MEM_VIRT       0xa0000000
+#define CONFIG_SYS_PCI2_MEM_BUS        0xa0000000
+#define CONFIG_SYS_PCI2_MEM_PHYS       0xa0000000
 #define CONFIG_SYS_PCI2_MEM_SIZE       0x20000000      /* 512M */
-#define CONFIG_SYS_PCI2_IO_BASE        0x00000000
+#define CONFIG_SYS_PCI2_IO_VIRT        0xe2800000
+#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
 #define CONFIG_SYS_PCI2_IO_PHYS        0xe2800000
 #define CONFIG_SYS_PCI2_IO_SIZE        0x00100000      /* 1M */
 #endif
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_BASE      0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS      CONFIG_SYS_PCIE1_MEM_BASE
+#define CONFIG_SYS_PCIE1_MEM_VIRT      0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS       0xa0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xa0000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE      0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_VIRT       0xe3000000
+#define CONFIG_SYS_PCIE1_IO_BUS        0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS       0xe3000000
 #define CONFIG_SYS_PCIE1_IO_SIZE       0x00100000      /*   1M */
 #endif
@@ -397,7 +403,8 @@ extern unsigned long get_clock_freq(void);
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_RIO_MEM_BASE        0xC0000000
+#define CONFIG_SYS_RIO_MEM_VIRT        0xC0000000
+#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
 #define CONFIG_SYS_RIO_MEM_SIZE        0x20000000      /* 512M */
 #endif
 
@@ -419,11 +426,6 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 
-/* PCI view of System Memory */
-#define CONFIG_SYS_PCI_MEMORY_BUS      0x00000000
-#define CONFIG_SYS_PCI_MEMORY_PHYS     0x00000000
-#define CONFIG_SYS_PCI_MEMORY_SIZE     0x80000000
-
 #endif /* CONFIG_PCI */
 
 
@@ -492,6 +494,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI