Merge git://www.denx.de/git/u-boot

[platform/kernel/u-boot.git] / include / configs / MPC8548CDS.h

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 03ab976..680009d 100644 (file)
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -36,12 +36,12 @@
 #define CONFIG_MPC8548         1       /* MPC8548 specific */
 #define CONFIG_MPC8548CDS      1       /* MPC8548CDS board specific */
 
-#undef CONFIG_PCI
+#define CONFIG_PCI
 #define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
-#define CONFIG_DDR_2T_TIMING           /* Sets the 2T timing bit */
+#undef CONFIG_DDR_2T_TIMING            /* Sets the 2T timing bit */
 
 #define CONFIG_DDR_ECC                 /* only for ECC DDR module */
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER      /* DDR controller or DMA? */
@@ -326,32 +326,48 @@ extern unsigned long get_clock_freq(void);
 #define OF_TBCLK               (bd->bi_busfreq / 8)
 #define OF_STDOUT_PATH         "/soc8548@e0000000/serial@4600"
 
-/* I2C */
-#define CONFIG_HARD_I2C                        /* I2C with hardware support */
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C         /* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C                /* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
 #define CFG_I2C_SPEED          400000  /* I2C speed and slave address */
 #define CFG_I2C_EEPROM_ADDR    0x57
 #define CFG_I2C_SLAVE          0x7F
 #define CFG_I2C_NOPROBES        {0x69} /* Don't probe these addrs */
+#define CFG_I2C_OFFSET         0x3000
 
 /*
  * General PCI
- * Addresses are mapped 1-1.
+ * Memory space is mapped 1-1, but I/O space must start from 0.
  */
 #define CFG_PCI1_MEM_BASE      0x80000000
 #define CFG_PCI1_MEM_PHYS      CFG_PCI1_MEM_BASE
-#define CFG_PCI1_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI1_MEM_SIZE      0x10000000      /* 256M */
 #define CFG_PCI1_IO_BASE       0x00000000
 #define CFG_PCI1_IO_PHYS       0xe2000000
-#define CFG_PCI1_IO_SIZE       0x00100000      /* 1M */
+#define CFG_PCI1_IO_SIZE       0x00800000      /* 8M */
 
-#define CFG_PCI2_MEM_BASE      0xa0000000
+#define CFG_PCI2_MEM_BASE      0x90000000
 #define CFG_PCI2_MEM_PHYS      CFG_PCI2_MEM_BASE
-#define CFG_PCI2_MEM_SIZE      0x20000000      /* 512M */
+#define CFG_PCI2_MEM_SIZE      0x10000000      /* 256M */
 #define CFG_PCI2_IO_BASE       0x00000000
-#define CFG_PCI2_IO_PHYS       0xe2100000
-#define CFG_PCI2_IO_SIZE       0x00100000      /* 1M */
+#define CFG_PCI2_IO_PHYS       0xe2800000
+#define CFG_PCI2_IO_SIZE       0x00800000      /* 8M */
+
+#define CFG_PEX_MEM_BASE       0xa0000000
+#define CFG_PEX_MEM_PHYS       CFG_PEX_MEM_BASE
+#define CFG_PEX_MEM_SIZE       0x20000000      /* 512M */
+#define CFG_PEX_IO_BASE                0x00000000
+#define CFG_PEX_IO_PHYS                0xe3000000
+#define CFG_PEX_IO_SIZE                0x01000000      /* 16M */
 
+/*
+ * RapidIO MMU
+ */
+#define CFG_RIO_MEM_BASE       0xC0000000
+#define CFG_RIO_MEM_SIZE       0x20000000      /* 512M */
 
 #if defined(CONFIG_PCI)
 
@@ -381,7 +397,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_MPC85XX_TSEC2_NAME      "eTSEC1"
 #define CONFIG_MPC85XX_TSEC3   1
 #define CONFIG_MPC85XX_TSEC3_NAME      "eTSEC2"
-#define CONFIG_MPC85XX_TSEC4   1
+#undef CONFIG_MPC85XX_TSEC4
 #define CONFIG_MPC85XX_TSEC4_NAME      "eTSEC3"
 #undef CONFIG_MPC85XX_FEC