Merge branch 'Makefile' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / include / configs / MPC8540ADS.h

diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index 5ea7b25..6351925 100644 (file)
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -46,7 +46,7 @@
 #endif
 
 #define CONFIG_PCI
-#define CONFIG_TSEC_ENET               /* tsec ethernet support */
+#define CONFIG_TSEC_ENET               /* tsec ethernet support */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_SPD_EEPROM              /* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_DLL                 /* possible DLL fix needed */
@@ -87,9 +87,6 @@
 #define CONFIG_BTB                     /* toggle branch predition */
 #define CONFIG_ADDR_STREAMING          /* toggle addr streaming */
 
-#define CONFIG_BOARD_EARLY_INIT_F      1       /* Call board_pre_init */
-
-#undef CFG_DRAM_TEST                   /* memory test, takes time */
 #define CFG_MEMTEST_START      0x00200000      /* memtest region */
 #define CFG_MEMTEST_END                0x00400000
 
@@ -98,8 +95,9 @@
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CFG_CCSRBAR_DEFAULT    0xff700000      /* CCSRBAR Default */
+#define CFG_CCSRBAR_DEFAULT    0xff700000      /* CCSRBAR Default */
 #define CFG_CCSRBAR            0xe0000000      /* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS       CFG_CCSRBAR     /* physical addr of CCSRBAR */
 #define CFG_IMMR               CFG_CCSRBAR     /* PQII uses CFG_IMMR */
 
 
@@ -146,7 +144,7 @@
 #define CFG_FLASH_ERASE_TOUT   60000   /* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 
-#define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
+#define CFG_MONITOR_BASE       TEXT_BASE       /* start of monitor */
 
 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 #define CFG_RAMBOOT
@@ -154,7 +152,7 @@
 #undef  CFG_RAMBOOT
 #endif
 
-#define CFG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_DRIVER
 #define CFG_FLASH_CFI
 #define CFG_FLASH_EMPTY_INFO
 
@@ -267,16 +265,16 @@
 #define CFG_BCSR               (CFG_BR4_PRELIM & 0xffff8000)
 
 #define CONFIG_L1_INIT_RAM
-#define CFG_INIT_RAM_LOCK      1
+#define CFG_INIT_RAM_LOCK      1
 #define CFG_INIT_RAM_ADDR      0xe4010000      /* Initial RAM address */
-#define CFG_INIT_RAM_END       0x4000          /* End of used area in RAM */
+#define CFG_INIT_RAM_END       0x4000          /* End of used area in RAM */
 
-#define CFG_GBL_DATA_SIZE      128             /* num bytes initial data */
+#define CFG_GBL_DATA_SIZE      128             /* num bytes initial data */
 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 
-#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserved for malloc */
+#define CFG_MONITOR_LEN                (256 * 1024)    /* Reserve 256 kB for Mon */
+#define CFG_MALLOC_LEN         (128 * 1024)    /* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX     1
@@ -336,7 +334,7 @@
 #if defined(CONFIG_PCI)
 
 #define CONFIG_NET_MULTI
-#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
@@ -344,7 +342,7 @@
 #if !defined(CONFIG_PCI_PNP)
     #define PCI_ENET0_IOADDR   0xe0000000
     #define PCI_ENET0_MEMADDR  0xe0000000
-    #define PCI_IDSEL_NUMBER   0x0c    /* slot0->3(IDSEL)=12->15 */
+    #define PCI_IDSEL_NUMBER   0x0c    /* slot0->3(IDSEL)=12->15 */
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
@@ -356,7 +354,7 @@
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI       1
+#define CONFIG_NET_MULTI       1
 #endif
 
 #define CONFIG_MII             1       /* MII PHY management */