drivers/mtd: Move conditional compilation to Makefile

[platform/kernel/u-boot.git] / include / configs / MPC837XERDB.h

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 0d79aae..82b3353 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -32,6 +32,7 @@
 
 #define CONFIG_PCI     1
 
+#define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_MISC_INIT_R
 
 /*
@@ -107,7 +108,7 @@
 /* System Clock Configuration Register */
 #define CFG_SCCR_TSEC1CM       1               /* eTSEC1 clock mode (0-3) */
 #define CFG_SCCR_TSEC2CM       1               /* eTSEC2 clock mode (0-3) */
-#define CFG_SCCR_SATACM                SCCR_SATACM_1   /* SATA1-4 clock mode (0-3) */
+#define CFG_SCCR_SATACM                SCCR_SATACM_2   /* SATA1-4 clock mode (0-3) */
 
 /*
  * System IO Config
@@ -248,7 +249,7 @@
  * FLASH on the Local Bus
  */
 #define CFG_FLASH_CFI          /* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER   /* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER        /* use the CFI driver */
 #define CFG_FLASH_BASE         0xFE000000 /* FLASH base address */
 #define CFG_FLASH_SIZE         8 /* max FLASH size is 32M */
 
@@ -275,6 +276,25 @@
 #define CFG_FLASH_ERASE_TOUT   60000   /* Flash Erase Timeout (ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Flash Write Timeout (ms) */
 
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CFG_NAND_BASE          0xE0600000      /* 0xE0600000 */
+#define CFG_BR1_PRELIM         (CFG_NAND_BASE | \
+                                (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
+                                BR_PS_8 |              /* Port Size = 8 bit */ \
+                                BR_MS_FCM |            /* MSEL = FCM */ \
+                                BR_V)                  /* valid */
+#define CFG_OR1_PRELIM         (0xFFFF8000 |           /* length 32K */ \
+                                OR_FCM_CSCT | \
+                                OR_FCM_CST | \
+                                OR_FCM_CHT | \
+                                OR_FCM_SCY_1 | \
+                                OR_FCM_TRLX | \
+                                OR_FCM_EHTR)
+#define CFG_LBLAWBAR1_PRELIM   CFG_NAND_BASE
+#define CFG_LBLAWAR1_PRELIM    0x8000000E      /* 32KB  */
+
 /* Vitesse 7385 */
 
 #define CFG_VSC7385_BASE       0xF0000000
@@ -304,6 +324,11 @@
 #define CFG_NS16550_COM1       (CFG_IMMR+0x4500)
 #define CFG_NS16550_COM2       (CFG_IMMR+0x4600)
 
+/* SERDES */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1     0xe3000
+#define CONFIG_FSL_SERDES2     0xe3100
+
 /* Use the HUSH parser */
 #define CFG_HUSH_PARSER
 #ifdef CFG_HUSH_PARSER
@@ -313,6 +338,7 @@
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
 #define CONFIG_OF_BOARD_SETUP  1
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
 
 /* I2C */
 #define CONFIG_HARD_I2C                /* I2C with hardware support */
@@ -340,7 +366,7 @@
 #define CFG_PCI_MMIO_BASE      0x90000000
 #define CFG_PCI_MMIO_PHYS      CFG_PCI_MMIO_BASE
 #define CFG_PCI_MMIO_SIZE      0x10000000 /* 256M */
-#define CFG_PCI_IO_BASE                0xE0300000
+#define CFG_PCI_IO_BASE                0x00000000
 #define CFG_PCI_IO_PHYS                0xE0300000
 #define CFG_PCI_IO_SIZE                0x100000 /* 1M */
 
@@ -390,6 +416,29 @@
 #endif
 
 /*
+ * SATA
+ */
+#define CONFIG_LIBATA
+#define CONFIG_FSL_SATA
+
+#define CFG_SATA_MAX_DEVICE    2
+#define CONFIG_SATA1
+#define CFG_SATA1_OFFSET       0x18000
+#define CFG_SATA1              (CFG_IMMR + CFG_SATA1_OFFSET)
+#define CFG_SATA1_FLAGS                FLAGS_DMA
+#define CONFIG_SATA2
+#define CFG_SATA2_OFFSET       0x19000
+#define CFG_SATA2              (CFG_IMMR + CFG_SATA2_OFFSET)
+#define CFG_SATA2_FLAGS                FLAGS_DMA
+
+#ifdef CONFIG_FSL_SATA
+#define CONFIG_LBA48
+#define CONFIG_CMD_SATA
+#define CONFIG_DOS_PARTITION
+#define CONFIG_CMD_EXT2
+#endif
+
+/*
  * Environment
  */
 #ifndef CFG_RAMBOOT
@@ -475,6 +524,8 @@
  * MMU Setup
  */
 
+#define CONFIG_HIGH_BATS       1       /* High BATs supported */
+
 /* DDR: cache cacheable */
 #define CFG_SDRAM_LOWER                CFG_SDRAM_BASE
 #define CFG_SDRAM_UPPER                (CFG_SDRAM_BASE + 0x10000000)
@@ -565,6 +616,8 @@
 #define CONFIG_ETH1ADDR                00:04:9f:ef:04:02
 #endif
 
+#define CONFIG_HAS_FSL_DR_USB
+
 #define CONFIG_IPADDR          10.0.0.2
 #define CONFIG_SERVERIP                10.0.0.1
 #define CONFIG_GATEWAYIP       10.0.0.1
@@ -578,7 +631,7 @@
 #define CONFIG_UBOOTPATH       u-boot.bin      /* U-Boot image on TFTP server */
 #define CONFIG_FDTFILE         mpc8379_rdb.dtb
 
-#define CONFIG_LOADADDR                200000  /* default location for tftp and bootm */
+#define CONFIG_LOADADDR                500000  /* default location for tftp and bootm */
 #define CONFIG_BOOTDELAY       -1      /* -1 disables auto-boot */
 #define CONFIG_BAUDRATE                115200