Merge tag 'efi-2019-07-rc3-3' of git://git.denx.de/u-boot-efi

[platform/kernel/u-boot.git] / include / configs / MPC837XERDB.h

diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index a1de8ac..13a7682 100644 (file)
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -23,13 +23,6 @@
 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */
 
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT  3       /* Arbiter repeat count (0-7) */
-
-/* System Priority Control Regsiter */
-#define CONFIG_SYS_SPCR_TSECEP 3       /* eTSEC1&2 emergency priority (0-3) */
-
 /* System Clock Configuration Register */
 #define CONFIG_SYS_SCCR_TSEC1CM        1               /* eTSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM        1               /* eTSEC2 clock mode (0-3) */
@@ -47,11 +40,6 @@
 #define CONFIG_SYS_OBIR                0x30100000
 
 /*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
-/*
  * Device configurations
  */
 
@@ -70,9 +58,7 @@
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 
@@ -172,12 +158,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET     \
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR            0x00000000
 #define CONFIG_FSL_ELBC                1
 
 /*
@@ -188,16 +168,6 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* display empty sectors */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_9 \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFF800191 */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256 /* max sectors per device */
@@ -210,38 +180,15 @@
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
+
+
 /* Vitesse 7385 */
 
 #define CONFIG_SYS_VSC7385_BASE        0xF0000000
 
 #ifdef CONFIG_VSC7385_ENET
 
-#define CONFIG_SYS_BR2_PRELIM          (CONFIG_SYS_VSC7385_BASE \
-                                       | BR_PS_8 \
-                                       | BR_MS_GPCM \
-                                       | BR_V)
-                                       /* 0xF0000801 */
-#define CONFIG_SYS_OR2_PRELIM          (OR_AM_128KB \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_SETA \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-                                       /* 0xfffe09ff */
+
 #endif
 
 /*
@@ -415,14 +362,6 @@
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK \
-                               | HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2                HID2_HBE
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
 #endif