* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
-#define CONFIG_MPC83XX 1 /* MPC83XX family */
-#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
+#define CONFIG_MPC83xx 1 /* MPC83xx family */
+#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
+#define CONFIG_SYS_TEXT_BASE 0xFE000000
+
/*
* System Clock Setup
*/
#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HWCONFIG
/*
* IMMR new address
/*
* The reserved memory
*/
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#endif
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
/*
/*
* Local Bus Configuration & Clock Setup
*/
-#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
+#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
#define CONFIG_SYS_LBC_LBCR 0x00000000
+#define CONFIG_FSL_ELBC 1
/*
* FLASH on the Local Bus
/*
* NAND Flash on the Local Bus
*/
+#define CONFIG_CMD_NAND 1
+#define CONFIG_MTD_NAND_VERIFY_WRITE 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_NAND_FSL_ELBC 1
+
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
- | OR_FCM_CSCT \
+ | OR_FCM_BCTLD \
| OR_FCM_CST \
| OR_FCM_CHT \
| OR_FCM_SCY_1 \
+ | OR_FCM_RST \
| OR_FCM_TRLX \
| OR_FCM_EHTR )
- /* 0xFFFF8396 */
+ /* 0xFFFF919E */
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
+
#ifdef CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
+#ifndef __ASSEMBLY__
+extern int board_pci_host_broken(void);
+#endif
+#define CONFIG_PCIE
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
+#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
+
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_TSEC2_NAME "eTSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 3
+#define TSEC1_PHY_ADDR_SGMII 8
+#define TSEC2_PHY_ADDR_SGMII 4
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#endif
#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
+#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_MMC 1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
/*
* Miscellaneous configurable options
*/
/*
* For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
+ * have to be in the first 256 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
/*
* Core HID Setup
*/
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID0_INIT 0x000000000
+#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
+ HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2 HID2_HBE
/*
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#endif
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM 0x02 /* Software reboot */
-
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
-#define CONFIG_ETHADDR 00:E0:0C:00:83:79
#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
#endif
#define CONFIG_BAUDRATE 115200
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
+#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
"consoledev=ttyS0\0" \
"ramdiskaddr=1000000\0" \
"ramdiskfile=ramfs.83xx\0" \
- "fdtaddr=400000\0" \
+ "fdtaddr=780000\0" \
"fdtfile=mpc8379_mds.dtb\0" \
""
projects / platform / kernel / u-boot.git / blobdiff