projects / platform / kernel / u-boot.git / blobdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | inline | side by side
MX: serial_mxc: cleanup removing nasty #ifdef
[platform/kernel/u-boot.git] / include / configs / MPC837XEMDS.h
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 76e598d..d7ee405 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -128,7 +128,10 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
-#define CONFIG_SYS_DDRCDR_VALUE        0x80080001 /* ODT 150ohm on SoC */
+#define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_DHC_EN \
+                                       | DDRCDR_ODT \
+                                       | DDRCDR_Q_DRN)
+                                       /* 0x80080001 */ /* ODT 150ohm on SoC */
 
 #undef CONFIG_DDR_ECC          /* support DDR ECC function */
 #undef CONFIG_DDR_ECC_CMD      /* Use DDR ECC user commands */
@@ -147,10 +150,11 @@
 #define CONFIG_SYS_DDR_SIZE            512 /* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS        0x0000001f
 #define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
-                               | 0x00010000  /* ODT_WR to CSn */ \
-                               | CSCONFIG_ROW_BIT_14 \
-                               | CSCONFIG_COL_BIT_10)
-                               /* 0x80010202 */
+                       | CSCONFIG_ODT_RD_NEVER  /* ODT_RD to none */ \
+                       | CSCONFIG_ODT_WR_ONLY_CURRENT  /* ODT_WR to CSn */ \
+                       | CSCONFIG_ROW_BIT_14 \
+                       | CSCONFIG_COL_BIT_10)
+                       /* 0x80010202 */
 #define CONFIG_SYS_DDR_TIMING_3        0x00000000
 #define CONFIG_SYS_DDR_TIMING_0        ((0 << TIMING_CFG0_RWT_SHIFT) \
                                | (0 << TIMING_CFG0_WRT_SHIFT) \
@@ -239,19 +243,20 @@
 
                                        /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | (2 << BR_PS_SHIFT)    /* 16 bit port */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR0_PRELIM  ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+                               | BR_PS_16      /* 16 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
                                | OR_GPCM_EAD)
                                /* 0xFE000FF7 */
 
@@ -268,11 +273,22 @@
 #define CONFIG_SYS_BCSR                0xF8000000
                                        /* Access window base at BCSR base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_BCSR
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E /* Access window size 32K */
-
-                               /* Port size=8bit, MSEL=GPCM */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR1_PRELIM  0xFFFFE9f7 /* length 32K */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
+
+#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR \
+                               | BR_PS_8 \
+                               | BR_MS_GPCM \
+                               | BR_V)
+                               /* 0xF8000801 */
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
+                               | OR_GPCM_XAM \
+                               | OR_GPCM_CSNT \
+                               | OR_GPCM_XACS \
+                               | OR_GPCM_SCY_15 \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
+                               | OR_GPCM_EAD)
+                               /* 0xFFFFE9F7 */
 
 /*
  * NAND Flash on the Local Bus
@@ -282,13 +298,13 @@
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_NAND_FSL_ELBC   1
 
-#define CONFIG_SYS_NAND_BASE   0xE0600000      /* 0xE0600000 */
+#define CONFIG_SYS_NAND_BASE   0xE0600000
 #define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
+                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
                                | BR_PS_8               /* 8 bit port */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR3_PRELIM  (0xFFFF8000     /* length 32K */ \
+                               | BR_V)                 /* valid */
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
                                | OR_FCM_BCTLD \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -299,7 +315,7 @@
                                /* 0xFFFF919E */
 
 #define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */
+#define CONFIG_SYS_LBLAWAR3_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
 
 /*
  * Serial Port
@@ -564,7 +580,7 @@ extern int board_pci_host_broken(void);
 #define CONFIG_SYS_SDRAM_UPPER         (CONFIG_SYS_SDRAM_BASE + 0x10000000)
 
 #define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_LOWER \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM_LOWER \
                                | BATU_BL_256M \
@@ -574,7 +590,7 @@ extern int board_pci_host_broken(void);
 #define CONFIG_SYS_DBAT0U      CONFIG_SYS_IBAT0U
 
 #define CONFIG_SYS_IBAT1L      (CONFIG_SYS_SDRAM_UPPER \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT1U      (CONFIG_SYS_SDRAM_UPPER \
                                | BATU_BL_256M \
@@ -585,7 +601,7 @@ extern int board_pci_host_broken(void);
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT2L      (CONFIG_SYS_IMMR \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_CACHEINHIBIT \
                                | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U      (CONFIG_SYS_IMMR \
@@ -597,7 +613,7 @@ extern int board_pci_host_broken(void);
 
 /* BCSR: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT3L      (CONFIG_SYS_BCSR \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_CACHEINHIBIT \
                                | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT3U      (CONFIG_SYS_BCSR \
@@ -609,20 +625,20 @@ extern int board_pci_host_broken(void);
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT4L      (CONFIG_SYS_FLASH_BASE \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT4U      (CONFIG_SYS_FLASH_BASE \
                                | BATU_BL_32M \
                                | BATU_VS \
                                | BATU_VP)
 #define CONFIG_SYS_DBAT4L      (CONFIG_SYS_FLASH_BASE \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_CACHEINHIBIT \
                                | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT4U      CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT5U      (CONFIG_SYS_INIT_RAM_ADDR \
                                | BATU_BL_128K \
                                | BATU_VS \
@@ -633,7 +649,7 @@ extern int board_pci_host_broken(void);
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
 #define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI_MEM_PHYS \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI_MEM_PHYS \
                                | BATU_BL_256M \
@@ -643,7 +659,7 @@ extern int board_pci_host_broken(void);
 #define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
 #define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI_MMIO_PHYS \
-                               | BATL_PP_10 \
+                               | BATL_PP_RW \
                                | BATL_CACHEINHIBIT \
                                | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI_MMIO_PHYS \
Domain: System / Kernel;