Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

[platform/kernel/u-boot.git] / include / configs / MPC837XEMDS.h

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index aeb61a9..a2a2aad 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -25,8 +25,8 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300            1 /* E300 family */
-#define CONFIG_MPC83XX         1 /* MPC83XX family */
-#define CONFIG_MPC837X         1 /* MPC837X CPU specific */
+#define CONFIG_MPC83xx         1 /* MPC83xx family */
+#define CONFIG_MPC837x         1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XEMDS     1 /* MPC837XEMDS board specific */
 
 /*
@@ -111,6 +111,7 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
 #define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_HWCONFIG
 
 /*
  * IMMR new address
@@ -204,7 +205,7 @@
 #endif
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 
 /*
@@ -268,6 +269,11 @@
 /*
  * NAND Flash on the Local Bus
  */
+#define CONFIG_CMD_NAND                1
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_NAND_FSL_ELBC   1
+
 #define CONFIG_SYS_NAND_BASE           0xE0600000      /* 0xE0600000 */
 #define CONFIG_SYS_BR3_PRELIM          ( CONFIG_SYS_NAND_BASE \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
@@ -275,13 +281,14 @@
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V )                /* valid */
 #define CONFIG_SYS_OR3_PRELIM          ( 0xFFFF8000            /* length 32K */ \
-                               | OR_FCM_CSCT \
+                               | OR_FCM_BCTLD \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
                                | OR_FCM_SCY_1 \
+                               | OR_FCM_RST \
                                | OR_FCM_TRLX \
                                | OR_FCM_EHTR )
-                               /* 0xFFFF8396 */
+                               /* 0xFFFF919E */
 
 #define CONFIG_SYS_LBLAWBAR3_PRELIM    CONFIG_SYS_NAND_BASE
 #define CONFIG_SYS_LBLAWAR3_PRELIM     0x8000000E      /* 32KB  */
@@ -313,6 +320,9 @@
 #define CONFIG_OF_BOARD_SETUP  1
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
+#define CONFIG_SYS_64BIT_STRTOUL               1
+#define CONFIG_SYS_64BIT_VSPRINTF              1
+
 /* I2C */
 #define CONFIG_HARD_I2C                /* I2C with hardware support */
 #undef CONFIG_SOFT_I2C         /* I2C bit-banged */
@@ -347,10 +357,35 @@
 #define CONFIG_SYS_PCI_SLV_MEM_BUS     0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE    0x80000000
 
+#define CONFIG_SYS_PCIE1_BASE          0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE      0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE      0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE      0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE          0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE      0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE      0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE      0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000
+
 #ifdef CONFIG_PCI
-#define CONFIG_83XX_GENERIC_PCI        1 /* Use generic PCI setup */
+#ifndef __ASSEMBLY__
+extern int board_pci_host_broken(void);
+#endif
+#define CONFIG_PCIE
 #define CONFIG_PQ_MDS_PIB      1 /* PQ MDS Platform IO Board */
 
+#define CONFIG_HAS_FSL_DR_USB  1 /* fixup device tree for the DR USB */
+
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
 
@@ -382,6 +417,8 @@
 #define CONFIG_TSEC2_NAME      "eTSEC1"
 #define TSEC1_PHY_ADDR         2
 #define TSEC2_PHY_ADDR         3
+#define TSEC1_PHY_ADDR_SGMII   8
+#define TSEC2_PHY_ADDR_SGMII   4
 #define TSEC1_PHYIDX           0
 #define TSEC2_PHYIDX           0
 #define TSEC1_FLAGS            (TSEC_GIGABIT | TSEC_REDUCED)
@@ -460,7 +497,7 @@
 #endif
 
 #if defined(CONFIG_SYS_RAMBOOT)
-    #undef CONFIG_CMD_ENV
+    #undef CONFIG_CMD_SAVEENV
     #undef CONFIG_CMD_LOADS
 #endif
 
@@ -468,6 +505,18 @@
 
 #undef CONFIG_WATCHDOG         /* watchdog disabled */
 
+#define CONFIG_MMC     1
+
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR      CONFIG_SYS_MPC83xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
 /*
  * Miscellaneous configurable options
  */