Merge tag 'efi-2020-07-rc2-3' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

[platform/kernel/u-boot.git] / include / configs / MPC837XEMDS.h

diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 9d6dc76..1254b4f 100644 (file)
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -12,13 +12,6 @@
  */
 #define CONFIG_E300            1 /* E300 family */
 
-/* Arbiter Configuration Register */
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT  3       /* Arbiter repeat count is 4 */
-
-/* System Priority Control Register */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
-
 /*
  * IP blocks clock configuration
  */
@@ -40,16 +33,9 @@
 #define CONFIG_HWCONFIG
 
 /*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
-/*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_83XX_DDR_USES_CS0
 #define CONFIG_SYS_DDRCDR_VALUE                (DDRCDR_DHC_EN \
@@ -121,8 +107,6 @@
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START       0x00040000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END         0x00140000
 
 /*
  * The reserved memory
@@ -149,33 +133,11 @@
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
-#define CONFIG_SYS_LBC_LBCR            0x00000000
-#define CONFIG_FSL_ELBC                1
-
-/*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_BASE  0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE  32 /* max FLASH size is 32M */
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | BR_PS_16      /* 16 bit port */ \
-                               | BR_MS_GPCM    /* MSEL = GPCM */ \
-                               | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
-                               | OR_UPM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_ACS_DIV2 \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFE000FF7 */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT      256 /* max sectors per device */
@@ -189,20 +151,6 @@
  */
 #define CONFIG_SYS_BCSR                0xF8000000
                                        /* Access window base at BCSR base */
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_BCSR \
-                               | BR_PS_8 \
-                               | BR_MS_GPCM \
-                               | BR_V)
-                               /* 0xF8000801 */
-#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB \
-                               | OR_GPCM_XAM \
-                               | OR_GPCM_CSNT \
-                               | OR_GPCM_XACS \
-                               | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX_SET \
-                               | OR_GPCM_EHTR_SET \
-                               | OR_GPCM_EAD)
-                               /* 0xFFFFE9F7 */
 
 /*
  * NAND Flash on the Local Bus
@@ -211,20 +159,7 @@
 #define CONFIG_NAND_FSL_ELBC   1
 
 #define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR3_PRELIM  (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR3_PRELIM  (OR_AM_32KB \
-                               | OR_FCM_BCTLD \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_RST \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF919E */
+
 
 /*
  * Serial Port
@@ -360,15 +295,6 @@ extern int board_pci_host_broken(void);
 /*
  * Environment
  */
-#ifndef CONFIG_SYS_RAMBOOT
-       #define CONFIG_ENV_ADDR         \
-                       (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-       #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
-       #define CONFIG_ENV_SIZE         0x2000
-#else
-       #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
-       #define CONFIG_ENV_SIZE         0x2000
-#endif
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
@@ -402,14 +328,6 @@ extern int board_pci_host_broken(void);
 #define CONFIG_SYS_BOOTMAPSZ   (256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE)
-#define CONFIG_SYS_HID2                HID2_HBE
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
 #endif