hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c

[platform/kernel/u-boot.git] / include / configs / MPC8360ERDK.h

diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 04ea738..5aad4fd 100644 (file)
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -96,7 +96,10 @@
 /*
  * DDRCDR - DDR Control Driver Register
  */
-#define CONFIG_SYS_DDRCDR_VALUE        0x80080001
+#define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_DHC_EN \
+                               | DDRCDR_ODT \
+                               | DDRCDR_Q_DRN)
+                               /* 0x80080001 */
 
 #undef CONFIG_SPD_EEPROM       /* Do not use SPD EEPROM for DDR setup */
 
@@ -105,11 +108,11 @@
  */
 #define CONFIG_DDR_II
 #define CONFIG_SYS_DDR_SIZE            256 /* MB */
-#define CONFIG_SYS_DDR_CS0_BNDS        0x0000000f
+#define CONFIG_SYS_DDR_CS0_BNDS                0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
                                        | CSCONFIG_ROW_BIT_13 \
                                        | CSCONFIG_COL_BIT_10 \
-                                       | CSCONFIG_ODT_WR_ACS)
+                                       | CSCONFIG_ODT_WR_ONLY_CURRENT)
 #define CONFIG_SYS_DDR_SDRAM_CFG       (SDRAM_CFG_SDRAM_TYPE_DDR2 \
                                        | SDRAM_CFG_ECC_EN)
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00001000
@@ -195,19 +198,20 @@
 
                                        /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     0x80000018 /* 32MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_32MB)
 
 #define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE \
-                               | (2 << BR_PS_SHIFT) /* 16 bit port */ \
-                               | BR_V) /* valid */
-#define CONFIG_SYS_OR0_PRELIM  ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+                               | BR_PS_16      /* 16 bit port */ \
+                               | BR_MS_GPCM    /* MSEL = GPCM */ \
+                               | BR_V)         /* valid */
+#define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
                                | OR_UPM_XAM \
                                | OR_GPCM_CSNT \
                                | OR_GPCM_ACS_DIV2 \
                                | OR_GPCM_XACS \
                                | OR_GPCM_SCY_15 \
-                               | OR_GPCM_TRLX \
-                               | OR_GPCM_EHTR \
+                               | OR_GPCM_TRLX_SET \
+                               | OR_GPCM_EHTR_SET \
                                | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
@@ -225,11 +229,20 @@
 #define CONFIG_MTD_NAND_VERIFY_WRITE
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000001b /* Access window size 4K */
+/*
+ * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
+ * ... What's correct?
+ */
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_256MB)
 
 /* Port size 8 bit, UPMA */
-#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_NAND_BASE | 0x00000881)
-#define CONFIG_SYS_OR1_PRELIM          0xfc000001
+#define CONFIG_SYS_BR1_PRELIM          (CONFIG_SYS_NAND_BASE \
+                                       | BR_PS_8 \
+                                       | BR_MS_UPMA \
+                                       | BR_V)
+                                       /* 0x60000881 */
+#define CONFIG_SYS_OR1_PRELIM          (OR_AM_64MB | OR_UPM_EAD)
+                                       /* 0xFC000001 */
 
 /*
  * Fujitsu MB86277 (MINT) graphics controller
@@ -237,12 +250,16 @@
 #define CONFIG_SYS_VIDEO_BASE          0x70000000
 
 #define CONFIG_SYS_LBLAWBAR2_PRELIM    CONFIG_SYS_VIDEO_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM     0x80000019 /* Access window size 64MB */
+#define CONFIG_SYS_LBLAWAR2_PRELIM     (LBLAWAR_EN | LBLAWAR_64MB)
 
 /* Port size 32 bit, UPMB */
-                               /* PS=11, UPMB */
-#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_VIDEO_BASE | 0x000018a1)
-#define CONFIG_SYS_OR2_PRELIM  0xfc000001 /* (64MB, EAD=1) */
+#define CONFIG_SYS_BR2_PRELIM  (CONFIG_SYS_VIDEO_BASE \
+                               | BR_PS_32 \
+                               | BR_MS_UPMB \
+                               | BR_V)
+                               /* 0x000018a1 */
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_64MB | OR_UPM_EAD)
+                               /* 0xFC000001 */
 
 /*
  * Serial Port
@@ -263,9 +280,6 @@
 #define CONFIG_AUTO_COMPLETE           /* add autocompletion support */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1