Merge branch 'master' of git://git.denx.de/u-boot-blackfin

[platform/kernel/u-boot.git] / include / configs / MPC8360EMDS.h

diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index aaff93f..d4c82cd 100644 (file)
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -1,22 +1,9 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006,2011 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -39,6 +26,18 @@
 /*
  * System Clock Setup
  */
+#ifdef CONFIG_CLKIN_33MHZ
+#ifdef CONFIG_PCISLAVE
+#define CONFIG_83XX_PCICLK     33330000 /* in HZ */
+#else
+#define CONFIG_83XX_CLKIN      33330000 /* in Hz */
+#endif
+
+#ifndef CONFIG_SYS_CLK_FREQ
+#define CONFIG_SYS_CLK_FREQ    33330000
+#endif
+
+#elif defined(CONFIG_CLKIN_66MHZ)
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_83XX_PCICLK     66000000 /* in HZ */
 #else
@@ -48,10 +47,24 @@
 #ifndef CONFIG_SYS_CLK_FREQ
 #define CONFIG_SYS_CLK_FREQ    66000000
 #endif
+#else
+#error Unknown oscillator frequency.
+#endif
 
 /*
  * Hardware Reset Configuration Word
  */
+#ifdef CONFIG_CLKIN_33MHZ
+#define CONFIG_SYS_HRCW_LOW (\
+       HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+       HRCWL_DDR_TO_SCB_CLK_1X1 |\
+       HRCWL_CSB_TO_CLKIN_8X1 |\
+       HRCWL_VCO_1X2 |\
+       HRCWL_CE_PLL_VCO_DIV_4 |\
+       HRCWL_CE_PLL_DIV_1X1 |\
+       HRCWL_CE_TO_PLL_1X15 |\
+       HRCWL_CORE_TO_CSB_2X1)
+#elif defined(CONFIG_CLKIN_66MHZ)
 #define CONFIG_SYS_HRCW_LOW (\
        HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
        HRCWL_DDR_TO_SCB_CLK_1X1 |\
@@ -61,6 +74,7 @@
        HRCWL_CE_PLL_DIV_1X1 |\
        HRCWL_CE_TO_PLL_1X6 |\
        HRCWL_CORE_TO_CSB_2X1)
+#endif
 
 #ifdef CONFIG_PCISLAVE
 #define CONFIG_SYS_HRCW_HIGH (\
@@ -145,9 +159,10 @@
 #define CONFIG_SYS_DDR_SDRAM_CFG       0x43000000
 #define CONFIG_SYS_DDR_SDRAM_CFG2      0x00401000
 #else
-#define CONFIG_SYS_DDR_CONFIG  (CSCONFIG_EN \
-                               | CSCONFIG_ROW_BIT_13 \
-                               | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS0_CONFIG      (CSCONFIG_EN \
+                                       | CSCONFIG_ROW_BIT_13 \
+                                       | CSCONFIG_COL_BIT_9)
+#define CONFIG_SYS_DDR_CS1_CONFIG      CONFIG_SYS_DDR_CS0_CONFIG
 #define CONFIG_SYS_DDR_TIMING_1        0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
 #define CONFIG_SYS_DDR_TIMING_2        0x00000800 /* may need tuning */
 #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
@@ -177,7 +192,7 @@
 
 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN  (128 * 1024) /* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN  (256 * 1024) /* Reserved for malloc */
 
 /*
  * Initial RAM Base Address Setup
@@ -388,9 +403,6 @@
 #define CONFIG_AUTO_COMPLETE           /* add autocompletion support   */
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
 
 /* pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -398,14 +410,12 @@
 #define CONFIG_OF_STDOUT_VIA_ALIAS     1
 
 /* I2C */
-#define CONFIG_HARD_I2C                /* I2C with hardware support */
-#undef CONFIG_SOFT_I2C         /* I2C bit-banged */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED   400000  /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE   0x7F
-#define CONFIG_SYS_I2C_NOPROBES        {0x52} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET  0x3000
-#define CONFIG_SYS_I2C2_OFFSET 0x3100
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED       400000
+#define CONFIG_SYS_FSL_I2C_SLAVE       0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET      0x3000
+#define CONFIG_SYS_I2C_NOPROBES                { {0, 0x52} }
 
 /*
  * Config on-board RTC
@@ -433,6 +443,7 @@
 
 
 #ifdef CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
 
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
 #define CONFIG_83XX_PCI_STREAMING
@@ -533,7 +544,6 @@
  */
 #define CONFIG_SYS_LONGHELP            /* undef to save memory */
 #define CONFIG_SYS_LOAD_ADDR           0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT              "=> "   /* Monitor Command Prompt */
 
 #if defined(CONFIG_CMD_KGDB)
        #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
@@ -546,7 +556,6 @@
 #define CONFIG_SYS_MAXARGS     16      /* max number of command args */
                                /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
-#define CONFIG_SYS_HZ          1000    /* decrementer freq: 1ms ticks */
 
 /*
  * For booting Linux, the board info and command line data
@@ -568,6 +577,7 @@
  */
 
 #define CONFIG_HIGH_BATS       1       /* High BATs supported */
+#define CONFIG_BAT_RW
 
 /* DDR/LBC SDRAM: cacheable */
 #define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM_BASE \
@@ -673,7 +683,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE   230400  /* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX  2       /* which serial port to use */
 #endif
 
 /*