video: Moving mx3fb.c to CONFIG_VIDEO

[platform/kernel/u-boot.git] / include / configs / MPC8349EMDS.h

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 5ac20f2..865d317 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -78,6 +78,22 @@
 #define CONFIG_SPD_EEPROM              /* use SPD EEPROM for DDR setup*/
 
 /*
+ * define CONFIG_FSL_DDR2 to use unified DDR driver
+ * undefine it to use old spd_sdram.c
+ */
+#define CONFIG_FSL_DDR2
+#ifdef CONFIG_FSL_DDR2
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1    0x52
+#define SPD_EEPROM_ADDRESS2    0x51
+#define CONFIG_NUM_DDR_CONTROLLERS     1
+#define CONFIG_DIMM_SLOTS_PER_CTLR     2
+#define CONFIG_CHIP_SELECTS_PER_CTRL   (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE  0xDeadBeef
+#endif
+
+/*
  * 32-bit data path mode.
  *
  * Please note that using this mode for devices with the real density of 64-bit
@@ -195,8 +211,7 @@
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFD000000              /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE       0x1000                  /* Size of used area in RAM*/
 
-#define CONFIG_SYS_GBL_DATA_SIZE       0x100                   /* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN         (384 * 1024)            /* Reserve 384 kB for Mon */
@@ -371,7 +386,6 @@
 #undef PCI_ONE_PCI1
 #endif
 
-#define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */
 #define CONFIG_83XX_PCI_STREAMING
 
@@ -395,9 +409,6 @@
 #define CONFIG_TSEC_ENET               /* TSEC ethernet support */
 
 #if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI       1
-#endif
 
 #define CONFIG_GMII            1       /* MII PHY management */
 #define CONFIG_TSEC1   1