#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
+ * define CONFIG_FSL_DDR2 to use unified DDR driver
+ * undefine it to use old spd_sdram.c
+ */
+#define CONFIG_FSL_DDR2
+#ifdef CONFIG_FSL_DDR2
+#define CONFIG_SYS_SPD_BUS_NUM 0
+#define SPD_EEPROM_ADDRESS1 0x52
+#define SPD_EEPROM_ADDRESS2 0x51
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
+#endif
+
+/*
* 32-bit data path mode.
*
* Please note that using this mode for devices with the real density of 64-bit
#undef PCI_ONE_PCI1
#endif
-#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
-#ifndef CONFIG_NET_MULTI
-#define CONFIG_NET_MULTI 1
-#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_TSEC1 1