Merge tag 'u-boot-rockchip-20190809' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / include / configs / MPC8349EMDS.h

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 3e0907d..7352e34 100644 (file)
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -17,8 +17,6 @@
  */
 #define CONFIG_E300            1       /* E300 Family */
 
-#define CONFIG_SYS_IMMR                0xE0000000
-
 #undef CONFIG_SYS_DRAM_TEST            /* memory test, takes time */
 #define CONFIG_SYS_MEMTEST_START       0x00000000      /* memtest region */
 #define CONFIG_SYS_MEMTEST_END         0x00100000
@@ -54,9 +52,7 @@
  */
 #undef CONFIG_DDR_32BIT
 
-#define CONFIG_SYS_DDR_BASE    0x00000000      /* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE  CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE  0x00000000      /* DDR is system memory*/
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  (DDR_SDRAM_CLK_CNTL_SS_EN \
                                        | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 #undef  CONFIG_DDR_2T_TIMING
@@ -158,16 +154,6 @@
 #define CONFIG_SYS_MALLOC_LEN  (256 * 1024)    /* Reserved for malloc */
 
 /*
- * Local Bus LCRR and LBCR regs
- *    LCRR:  DLL bypass, Clock divider is 4
- * External Local Bus rate is
- *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
-#define CONFIG_SYS_LBC_LBCR    0x00000000
-
-/*
  * Serial Port
  */
 #define CONFIG_SYS_NS16550_SERIAL
@@ -330,10 +316,6 @@
 /*
  * System performance
  */
-#define CONFIG_SYS_ACR_PIPE_DEP        3       /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT  3       /* Arbiter repeat count (0-7) */
-#define CONFIG_SYS_SPCR_TSEC1EP        3       /* TSEC1 emergency priority (0-3) */
-#define CONFIG_SYS_SPCR_TSEC2EP        3       /* TSEC2 emergency priority (0-3) */
 #define CONFIG_SYS_SCCR_TSEC1CM        1       /* TSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM        1       /* TSEC2 & I2C0 clock mode (0-3) */
 
@@ -341,17 +323,6 @@
 #define CONFIG_SYS_SICRH 0
 #define CONFIG_SYS_SICRL SICRL_LDP_A
 
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK \
-                               | HID0_ENABLE_INSTRUCTION_CACHE)
-
-/* #define CONFIG_SYS_HID0_FINAL       (\
-       HID0_ENABLE_INSTRUCTION_CACHE |\
-       HID0_ENABLE_M_BIT |\
-       HID0_ENABLE_ADDRESS_BROADCAST) */
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE
 #endif
@@ -376,10 +347,6 @@
 
 #define CONFIG_LOADADDR        800000  /* default location for tftp and bootm */
 
-#define CONFIG_PREBOOT "echo;" \
-       "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-       "echo"
-
 #define        CONFIG_EXTRA_ENV_SETTINGS                                       \
        "netdev=eth0\0"                                                 \
        "hostname=mpc8349emds\0"                                        \