+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2006-2010
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_DISPLAY_BOARDINFO
-
/*
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 Family */
-#define CONFIG_MPC834x 1 /* MPC834x family */
-#define CONFIG_MPC8349 1 /* MPC8349 specific */
-#define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
#define CONFIG_PCI_66M
#ifdef CONFIG_PCI_66M
#endif
#ifdef CONFIG_PCISLAVE
-#define CONFIG_PCI
#define CONFIG_83XX_PCICLK 66666666 /* in Hz */
#endif /* CONFIG_PCISLAVE */
#endif
#endif
-#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
-
#define CONFIG_SYS_IMMR 0xE0000000
#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
/*
- * define CONFIG_SYS_FSL_DDR2 to use unified DDR driver
- * undefine it to use old spd_sdram.c
+ * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
+ * unselect it to use old spd_sdram.c
*/
-#define CONFIG_SYS_FSL_DDR2
-#ifdef CONFIG_SYS_FSL_DDR2
-#define CONFIG_SYS_FSL_DDRC_GEN2
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS1 0x52
#define SPD_EEPROM_ADDRESS2 0x51
-#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 2
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-#endif
/*
* 32-bit data path mode.
/*
* FLASH on the Local Bus
*/
-#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
-/* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| BR_PS_16 /* 16 bit port */ \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
/*
#define CONFIG_SYS_LBC_LBCR 0x00000000
/*
- * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory.
- * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM
- */
-#undef CONFIG_SYS_LB_SDRAM
-
-#ifdef CONFIG_SYS_LB_SDRAM
-/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */
-/*
- * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
- *
- * For BR2, need:
- * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
- * port-size = 32-bits = BR2[19:20] = 11
- * no parity checking = BR2[21:22] = 00
- * SDRAM for MSEL = BR2[24:26] = 011
- * Valid = BR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861
- */
-
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \
- | BR_PS_32 /* 32-bit port */ \
- | BR_MS_SDRAM /* MSEL = SDRAM */ \
- | BR_V) /* Valid */
- /* 0xF0001861 */
-#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE
-#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
-
-/*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
- *
- * For OR2, need:
- * 64MB mask for AM, OR2[0:7] = 1111 1100
- * XAM, OR2[17:18] = 11
- * 9 columns OR2[19-21] = 010
- * 13 rows OR2[23-25] = 100
- * EAD set for extra time OR[31] = 1
- *
- * 0 4 8 12 16 20 24 28
- * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901
- */
-
-#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \
- | OR_SDRAM_XAM \
- | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \
- | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \
- | OR_SDRAM_EAD)
- /* 0xFC006901 */
-
- /* LB sdram refresh timer, about 6us */
-#define CONFIG_SYS_LBC_LSRT 0x32000000
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \
- | LSDMR_BSMA1516 \
- | LSDMR_RFCR8 \
- | LSDMR_PRETOACT6 \
- | LSDMR_ACTTORW3 \
- | LSDMR_BL8 \
- | LSDMR_WRC3 \
- | LSDMR_CL3)
-
-/*
- * SDRAM Controller configuration sequence.
- */
-#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
-#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
-#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
-#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
-#endif
-
-/*
* Serial Port
*/
-#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
/* SPI */
-#define CONFIG_MPC8XXX_SPI
#undef CONFIG_SOFT_SPI /* SPI bit-banged */
/* GPIOs. Used as SPI chip selects */
#if defined(CONFIG_PCI)
-#define PCI_ONE_PCI1
-#if defined(PCI_64BIT)
-#undef PCI_ALL_PCI1
-#undef PCI_TWO_PCI1
-#undef PCI_ONE_PCI1
-#endif
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_83XX_PCI_STREAMING
#undef CONFIG_EEPRO100
/*
* TSEC configuration
*/
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
#if defined(CONFIG_TSEC_ENET)
* Environment
*/
#ifndef CONFIG_SYS_RAMBOOT
- #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
/*
* BOOTP options
*/
#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
/*
* Command line configuration.
*/
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_MII
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
#undef CONFIG_WATCHDOG /* watchdog disabled */
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-
- /* Print Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
/*
* For booting Linux, the board info and command line data
* have to be in the first 256 MB of memory, since this is
*/
/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
#else
-#if defined(PCI_64BIT)
+#if defined(CONFIG_PCI_64BIT)
#define CONFIG_SYS_HRCW_HIGH (\
HRCWH_PCI_HOST |\
HRCWH_64_BIT_PCI |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_TSEC1M_IN_GMII |\
HRCWH_TSEC2M_IN_GMII)
-#endif /* PCI_64BIT */
+#endif /* CONFIG_PCI_64BIT */
#endif /* CONFIG_PCISLAVE */
/*
HID0_ENABLE_M_BIT |\
HID0_ENABLE_ADDRESS_BROADCAST) */
-
#define CONFIG_SYS_HID2 HID2_HBE
#define CONFIG_HIGH_BATS 1 /* High BATs supported */
#define CONFIG_HAS_ETH0
#endif
-#define CONFIG_HOSTNAME mpc8349emds
+#define CONFIG_HOSTNAME "mpc8349emds"
#define CONFIG_ROOTPATH "/nfsroot/rootfs"
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
-#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
-#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE 115200
-
#define CONFIG_PREBOOT "echo;" \
"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
"echo"
projects / platform / kernel / u-boot.git / blobdiff