Merge git://git.denx.de/u-boot into u-boot

[platform/kernel/u-boot.git] / include / configs / MPC8315ERDB.h

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index add65f0..a04868e 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -166,7 +166,7 @@
 #undef CONFIG_SYS_RAMBOOT
 #endif
 
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN         (384 * 1024) /* Reserve 384 kB for Mon */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024) /* Reserved for malloc */
 
 /*
@@ -223,15 +223,16 @@
  */
 #define CONFIG_SYS_NAND_BASE           0xE0600000      /* 0xE0600000 */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define NAND_MAX_CHIPS         1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_VERIFY_WRITE   1
+#define CONFIG_CMD_NAND                        1
+#define CONFIG_NAND_FSL_ELBC           1
 
-#define CONFIG_SYS_BR1_PRELIM          ( CONFIG_SYS_NAND_BASE \
+#define CONFIG_SYS_BR1_PRELIM  ( CONFIG_SYS_NAND_BASE \
                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
                                | BR_PS_8               /* Port Size = 8 bit */ \
                                | BR_MS_FCM             /* MSEL = FCM */ \
                                | BR_V )                /* valid */
-#define CONFIG_SYS_OR1_PRELIM          ( 0xFFFF8000            /* length 32K */ \
+#define CONFIG_SYS_OR1_PRELIM  ( 0xFFFF8000            /* length 32K */ \
                                | OR_FCM_CSCT \
                                | OR_FCM_CST \
                                | OR_FCM_CHT \
@@ -308,8 +309,29 @@
 #define CONFIG_SYS_PCI_SLV_MEM_BUS     0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE    0x80000000
 
+#define CONFIG_SYS_PCIE1_BASE          0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE      0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS      0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE      0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE      0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS       0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE       0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE          0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE      0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS      0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE      0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE      0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE      0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE       0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS       0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE       0x00800000
+
 #define CONFIG_PCI
 #define CONFIG_83XX_GENERIC_PCI        1 /* Use generic PCI setup */
+#define CONFIG_83XX_GENERIC_PCIE       1
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_PNP         /* do pci plug-and-play */