Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u...

[platform/kernel/u-boot.git] / include / configs / MPC8315ERDB.h

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index fb568ef..5085a95 100644 (file)
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -32,23 +32,9 @@
 #define CONFIG_HWCONFIG
 
 /*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR                0xE0000000
-
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP        3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT  3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
-
-/*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE            0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE      CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE          0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL  DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE        (DDRCDR_EN \
                                | DDRCDR_PZ_LOZ \
@@ -131,14 +117,6 @@
                        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP   LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV         LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR            0x00040000
-#define CONFIG_FSL_ELBC                1
-
-/*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI_WIDTH     FLASH_CFI_16BIT
@@ -146,10 +124,6 @@
 #define CONFIG_SYS_FLASH_BASE          0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE          8       /* FLASH size is 8M */
 
-                                       /* Window base at flash base */
-#define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_8MB)
-
 #define CONFIG_SYS_MAX_FLASH_BANKS     1 /* number of banks */
 /* 127 64KB sectors and 8 8KB top sectors per device */
 #define CONFIG_SYS_MAX_FLASH_SECT      135
@@ -181,44 +155,12 @@
 #define CONFIG_SYS_NAND_U_BOOT_OFFS  16384
 #define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
 
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
-                                       | BR_PS_16      /* 16 bit port */ \
-                                       | BR_MS_GPCM    /* MSEL = GPCM */ \
-                                       | BR_V)         /* valid */
-#define CONFIG_SYS_OR0_PRELIM (OR_AM_8MB \
-                                       | OR_UPM_XAM \
-                                       | OR_GPCM_CSNT \
-                                       | OR_GPCM_ACS_DIV2 \
-                                       | OR_GPCM_XACS \
-                                       | OR_GPCM_SCY_15 \
-                                       | OR_GPCM_TRLX_SET \
-                                       | OR_GPCM_EHTR_SET \
-                                       | OR_GPCM_EAD)
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
-                               | BR_DECC_CHK_GEN       /* Use HW ECC */ \
-                               | BR_PS_8               /* 8 bit port */ \
-                               | BR_MS_FCM             /* MSEL = FCM */ \
-                               | BR_V)                 /* valid */
-#define CONFIG_SYS_OR1_PRELIM \
-                               (OR_AM_32KB \
-                               | OR_FCM_CSCT \
-                               | OR_FCM_CST \
-                               | OR_FCM_CHT \
-                               | OR_FCM_SCY_1 \
-                               | OR_FCM_TRLX \
-                               | OR_FCM_EHTR)
-                               /* 0xFFFF8396 */
+
 
 /* Still needed for spl_minimal.c */
 #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM
 #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM
 
-#define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
-
 #if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
        !defined(CONFIG_NAND_SPL)
 #define CONFIG_SYS_RAMBOOT
@@ -355,15 +297,6 @@
 /*
  * Environment
  */
-#if !defined(CONFIG_SYS_RAMBOOT)
-       #define CONFIG_ENV_ADDR         \
-                       (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-       #define CONFIG_ENV_SECT_SIZE    0x10000 /* 64K(one sector) for env */
-       #define CONFIG_ENV_SIZE         0x2000
-#else
-       #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
-       #define CONFIG_ENV_SIZE         0x2000
-#endif
 
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE   1       /* allow baudrate change */
@@ -393,15 +326,6 @@
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 
 /*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT   0x000000000
-#define CONFIG_SYS_HID0_FINAL  (HID0_ENABLE_MACHINE_CHECK | \
-                                HID0_ENABLE_INSTRUCTION_CACHE | \
-                                HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2                HID2_HBE
-
-/*
  * MMU Setup
  */