* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
- *
- * History
- * 20061201: Wilson Lo (Wilson.Lo@freescale.com)
- * Initialized
- * 20061210: Tanya Jiang (tanya.jiang@freescale.com)
- * Code Cleanup
- * 20070410: Scott Wood <scottwood@freescale.com>
- * More cleanup
*/
/*
* mpc8313epb board configuration file
* seem to have the SPD connected to I2C.
*/
#define CFG_DDR_SIZE 128 /* MB */
-#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \
- | 0x00040000 /* TODO */ \
+#define CFG_DDR_CONFIG ( CSCONFIG_EN \
+ | 0x00010000 /* TODO */ \
| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
- /* 0x80840102 */
+ /* 0x80010102 */
#define CFG_DDR_TIMING_3 0x00000000
#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
/* 0x00220802 */
#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
- | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+ | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
- | (13 << TIMING_CFG1_REFREC_SHIFT ) \
+ | (10 << TIMING_CFG1_REFREC_SHIFT ) \
| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
- /* 0x3935d322 */
-#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
- | (31 << TIMING_CFG2_CPO_SHIFT ) \
+ /* 0x3835a322 */
+#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+ | ( 5 << TIMING_CFG2_CPO_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
- | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
- /* 0x0f9048ca */ /* P9-45,may need tuning */
-#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
- | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
- /* 0x03200064 */
+ | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+ /* 0x129048c6 */ /* P9-45,may need tuning */
+#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+ | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+ /* 0x05100500 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_2T_EN \
| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
- | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+ | SDRAM_CFG_SDRAM_TYPE_DDR2 \
| SDRAM_CFG_32_BE )
/* 0x43080000 */
#endif
#define CFG_SDRAM_CFG2 0x00401000;
/* set burst length to 8 for 32-bit data path */
-#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
- | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
- /* 0x44400232 */
+#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \
+ | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) )
+ /* 0x44480632 */
#define CFG_DDR_MODE_2 0x8000C000;
#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
-#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
- (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
- BR_V) /* valid */
-#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
+#define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* flash Base address */ \
+ (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+ BR_V) /* valid */
+#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
| OR_GPCM_XACS \
| OR_GPCM_SCY_9 \
| OR_GPCM_EHTR \
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
| (0xFF << LBCR_BMT_SHIFT) \
| 0xF ) /* 0x0004ff0f */
-#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
+#define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */
-/* drivers/nand/nand.c */
-#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
+/* drivers/mtd/nand/nand.c */
+#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
#define CFG_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
- | BR_PS_8 /* Port Size = 8 bit */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V ) /* valid */
-#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
+ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_PS_8 /* Port Size = 8 bit */ \
+ | BR_MS_FCM /* MSEL = FCM */ \
+ | BR_V ) /* valid */
+#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
/* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE 1
+#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
-
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE 8192
-
-#define OF_CPU "PowerPC,8313@0"
-#define OF_SOC "soc8313@e0000000"
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
+#define CONFIG_OF_STDOUT_VIA_ALIAS 1
/*
* Serial Port
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
#define CFG_I2C_SLAVE 0x7F
-#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
+#define CFG_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */
#define CFG_I2C_OFFSET 0x3000
#define CFG_I2C2_OFFSET 0x3100
#endif
#define CONFIG_GMII 1 /* MII PHY management */
-#define CONFIG_MPC83XX_TSEC1 1
+#define CONFIG_TSEC1 1
-#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
-#define CONFIG_MPC83XX_TSEC2 1
-#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
+#define CONFIG_TSEC1_NAME "TSEC0"
+#define CONFIG_TSEC2 1
+#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4
+#define TSEC1_FLAGS TSEC_GIGABIT
+#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
*/
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
- #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
+ #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \
- | CFG_CMD_PING \
- | CFG_CMD_DHCP \
- | CFG_CMD_I2C \
- | CFG_CMD_MII \
- | CFG_CMD_DATE \
- | CFG_CMD_PCI)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_CMDLINE_EDITING 1
-#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \
- ~(CFG_CMD_ENV | CFG_CMD_LOADS))
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_PCI
#if defined(CFG_RAMBOOT)
-#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
-#else
-#define CONFIG_COMMANDS CFG_BASE_COMMANDS
+ #undef CONFIG_CMD_ENV
+ #undef CONFIG_CMD_LOADS
#endif
-#include <cmd_confdefs.h>
+#define CONFIG_CMDLINE_EDITING 1
+
/*
* Miscellaneous configurable options
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
*/
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE 16384
-#define CFG_CACHELINE_SIZE 32
-#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
-
-#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
+#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
#ifdef CFG_66MHZ
HRCWH_LALE_NORMAL)
/* System IO Config */
-#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
-#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
+#define CFG_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */
+#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
#define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
- HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CFG_HID2 HID2_HBE
#define CONFIG_ETHADDR 00:E0:0C:00:95:01
#define CONFIG_HAS_ETH1
+#define CONFIG_HAS_ETH0
#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
#define CONFIG_IPADDR 10.0.0.2
projects / platform / kernel / u-boot.git / blobdiff