pci: introduce CONFIG_PCI_INDIRECT_BRIDGE option

[platform/kernel/u-boot.git] / include / configs / MPC8266ADS.h

diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index b0162c3..c5aa586 100644 (file)
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -33,7 +33,7 @@
 /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
    !!                                                                !!
    !!  This configuration requires JP3 to be in position 1-2 to work  !!
-   !!  To make it work for the default, the TEXT_BASE define in              !!
+   !!  To make it work for the default, the CONFIG_SYS_TEXT_BASE define in           !!
    !!  board/mpc8266ads/config.mk must be changed from 0xfe000000 to  !!
    !!  0xfff00000                                                    !!
    !!  The CONFIG_SYS_HRCW_MASTER define below must also be changed to match !!
@@ -53,6 +53,8 @@
 #define CONFIG_MPC8266ADS      1       /* ...on motorola ADS board     */
 #define CONFIG_CPM2            1       /* Has a CPM2 */
 
+#define        CONFIG_SYS_TEXT_BASE    0xfe000000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1    /* Call board_early_init_f      */
 #define CONFIG_RESET_PHY_R     1       /* Call reset_phy()             */
 
@@ -96,6 +98,10 @@
  * Port pins used for bit-banged MII communictions (if applicable).
  */
 #define MDIO_PORT      2       /* Port C */
+#define MDIO_DECLARE   volatile ioport_t *iop = ioport_addr ( \
+                               (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE    MDIO_DECLARE
+
 #define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
 #define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
 #define MDIO_READ      ((iop->pdat &  0x00400000) != 0)
@@ -116,8 +122,8 @@
  * - Select bus for bd/buffers (see 28-13)
  * - Half duplex
  */
-# define CONFIG_SYS_CMXFCR_MASK        (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
+# define CONFIG_SYS_CMXFCR_MASK2       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
+# define CONFIG_SYS_CMXFCR_VALUE2      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
 # define CONFIG_SYS_CPMFCR_RAMTYPE     0
 # define CONFIG_SYS_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
 
@@ -131,6 +137,7 @@
 
 /* PCI */
 #define CONFIG_PCI
+#define CONFIG_PCI_INDIRECT_BRIDGE
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_BOOTDELAY 0
 #undef CONFIG_PCI_SCAN_SHOW
@@ -376,9 +383,8 @@
 #define FETH_RST               0x04000004
 
 #define CONFIG_SYS_INIT_RAM_ADDR       CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       0x4000  /* Size of used area in DPRAM   */
+#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /* Use this HRCW for booting from address 0xfe00000 (JP3 in setting 1-2)  */
@@ -415,10 +421,8 @@
 #define CONFIG_SYS_HRCW_SLAVE6 0
 #define CONFIG_SYS_HRCW_SLAVE7 0
 
-#define BOOTFLAG_COLD  0x01    /* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM  0x02    /* Software reboot           */
+#define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 
-#define CONFIG_SYS_MONITOR_BASE    TEXT_BASE
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #   define CONFIG_SYS_RAMBOOT
 #endif