* Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
* Ported to MPC8272ADS board.
*
+ * Copyright (c) 2005 MontaVista Software, Inc.
+ * Vitaly Bordug <vbordug@ru.mvista.com>
+ * Added support for PCI bridge on MPC8272ADS
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
+
+/*
+ * Figure out if we are booting low via flash HRCW or high via the BCSR.
+ */
+#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
+# define CFG_LOWBOOT 1
+#endif
+
/* ADS flavours */
#define CFG_8260ADS 1 /* MPC8260ADS */
#define CFG_8266ADS 2 /* MPC8266ADS */
* for FCC)
*
* if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
*/
#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
#define CFG_MDIO_PIN 0x00002000 /* PC18 */
#define CFG_MDC_PIN 0x00001000 /* PC19 */
#else
-#define CFG_MDIO_PIN 0x00400000 /* PC9 */
+#define CFG_MDIO_PIN 0x00400000 /* PC9 */
#define CFG_MDC_PIN 0x00200000 /* PC10 */
#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
#define CFG_I2C_SLAVE 0x7F
#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR 0x50
+#define CONFIG_SPD_ADDR 0x50
#endif
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
+/*PCI*/
+#ifdef CONFIG_MPC8272
+#define CONFIG_PCI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_BOOTDELAY 0
+#define CONFIG_PCI_SCAN_SHOW
+#endif
+
#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
+#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
#endif
#ifndef CONFIG_8260_CLKIN
#endif
#endif
-#define CONFIG_BAUDRATE 38400
-
-#define CFG_EXCLUDE CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_KGDB | \
- CFG_CMD_MMC | \
- CFG_CMD_NAND | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_REISER | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_USB | \
- CFG_CMD_VFD
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DISPLAY
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_EXT2
+#undef CONFIG_CMD_FAT
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_SNTP
+#undef CONFIG_CMD_UNIVERSE
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_XIMG
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+
+#elif CONFIG_ADSTYPE >= CFG_PQ2FADS
+ #undef CONFIG_CMD_SDRAM
+ #undef CONFIG_CMD_I2C
+ #undef CONFIG_CMD_PCI
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_SDRAM | \
- CFG_CMD_I2C | \
- CFG_EXCLUDE ) )
#else
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_EXCLUDE ) )
+ #undef CONFIG_CMD_PCI
+
#endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
#endif
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
+#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
/*
* Miscellaneous configurable options
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CFG_LOAD_ADDR 0x400000 /* default load address */
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-#define CFG_JFFS2_FIRST_SECTOR 1
-#define CFG_JFFS2_LAST_SECTOR 27
+/*
+ * JFFS2 partitions
+ *
+ * Note: fake mtd_id used, no linux mtd map file
+ */
+#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
+#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
#define CFG_JFFS2_SORT_FRAGMENTS
-#define CFG_JFFS_CUSTOM_PART
/* this is stuff came out of the Motorola docs */
+#ifndef CFG_LOWBOOT
#define CFG_DEFAULT_IMMR 0x0F010000
+#endif
#define CFG_IMMR 0xF0000000
#define CFG_BCSR 0xF4500000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_PCI_INT 0xF8200000
+#endif
#define CFG_SDRAM_BASE 0x00000000
#define CFG_LSDRAM_BASE 0xFD000000
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
-/* 0x0EA28205 */
+#ifdef CFG_LOWBOOT
+/* PQ2FADS flash HRCW = 0x0EB4B645 */
+#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
+ ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
+ ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
+ ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
+ )
+#else
+/* PQ2FADS BCSR HRCW = 0x0CB23645 */
#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
( HRCW_BMS | HRCW_APPC10 ) |\
( HRCW_MODCK_H0101 ) \
)
+#endif
/* no slaves */
#define CFG_HRCW_SLAVE1 0
#define CFG_HRCW_SLAVE2 0
# define CFG_ENV_SIZE 0x200
#endif /* CFG_RAMBOOT */
-
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
-
#define CFG_HID0_INIT 0
#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801
#define CFG_OR1_PRELIM 0xFFFF8010
+/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */
+#define CFG_OR3_PRELIM 0xFFFF8010
+#endif
+
#define CFG_RMR RMR_CSRE
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
#define CFG_RESET_ADDRESS 0x04400000
+#if CONFIG_ADSTYPE == CFG_8272ADS
+
+/* PCI Memory map (if different from default map */
+#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
+#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
+#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
+ PICMR_PREFETCH_EN)
+
+/*
+ * These are the windows that allow the CPU to access PCI address space.
+ * All three PCI master windows, which allow the CPU to access PCI
+ * prefetch, non prefetch, and IO space (see below), must all fit within
+ * these windows.
+ */
+
+/*
+ * Master window that allows the CPU to access PCI Memory (prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
+#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
+#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
+#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
+
+/*
+ * Master window that allows the CPU to access PCI Memory (non-prefetch).
+ * This window will be setup with the second set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
+#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
+#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
+#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
+#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
+
+/*
+ * Master window that allows the CPU to access PCI IO space.
+ * This window will be setup with the first set of Outbound ATU registers
+ * in the bridge.
+ */
+
+#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
+#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
+#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
+#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
+#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
+
+
+/* PCIBR0 - for PCI IO*/
+#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */
+#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
+/* PCIBR1 - prefetch and non-prefetch regions joined together */
+#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL
+#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U)
+
+#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
+
+#if CONFIG_ADSTYPE == CFG_8272ADS
+#define CONFIG_HAS_ETH1
+#endif
+
#endif /* __CONFIG_H */
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