#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_MIP405 1 /* ...on a MIP405 board */
+
+#define CONFIG_SYS_TEXT_BASE 0xFFF80000
+
/***********************************************************
* Note that it may also be a MIP405T board which is a subset of the
* MIP405
/* reserve some memory for POST and BOOT limit info */
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
-#ifdef CONFIG_POST /* reserve one word for POST Info */
-#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4)
-#endif
-
#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12)
#endif