Re-factoring the legacy NAND code (legacy NAND now only in board-specific

[platform/kernel/u-boot.git] / include / configs / MIP405.h

diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index 41a3d39..1f01e7b 100644 (file)
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -87,6 +87,8 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
 #include <cmd_confdefs.h>
 
+#define CFG_NAND_LEGACY
+
 #define         CFG_HUSH_PARSER
 #define         CFG_PROMPT_HUSH_PS2 "> "
 /**************************************************************
@@ -128,7 +130,7 @@
 #define CONFIG_BAUDRATE                9600    /* STD Baudrate */
 #define CONFIG_BOOTDELAY       5
 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
-#define CONFIG_BOOT_RETRY_TIME -10     /* feature is avaiable but not enabled */
+/* #define CONFIG_BOOT_RETRY_TIME      -10     /XXX* feature is available but not enabled */
 #define CONFIG_ZERO_BOOTDELAY_CHECK    /* check console even if bootdelay = 0 */
 
 #define CONFIG_BOOTCOMMAND     "diskboot 400000 0:1; bootm" /* autoboot command                */
@@ -236,13 +238,28 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
-#define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV               "nor0"
+#define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET       0x00000000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT         "nor0=mip405-0"
+#define MTDPARTS_DEFAULT       "mtdparts=mip405-0:-(jffs2)"
+*/
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE                0x4000  /* For IBM 405GPr CPUs                  */
+#define CFG_DCACHE_SIZE                0x4000  /* For AMCC 405GPr CPUs                 */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */