hush.c: Move default CONFIG_SYS_PROMPT_HUSH_PS2 to hush.c

[platform/kernel/u-boot.git] / include / configs / MERGERBOX.h

diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h
index 100d6f7..077e0d0 100644 (file)
--- a/include/configs/MERGERBOX.h
+++ b/include/configs/MERGERBOX.h
@@ -159,11 +159,13 @@
 #define CONFIG_SYS_LBLAWBAR0_PRELIM    CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_LBLAWAR0_PRELIM     (LBLAWAR_EN | LBLAWAR_64MB)
 
-#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR0_PRELIM  (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\
+                                BR_MS_GPCM | BR_V)
 #define CONFIG_SYS_OR0_PRELIM  (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\
                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\
-                                OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\
-                                OR_GPCM_EHTR | OR_GPCM_EAD)
+                                OR_GPCM_XACS | OR_GPCM_SCY_15 |\
+                                OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\
+                                OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS     1
 #define CONFIG_SYS_MAX_FLASH_SECT      512
@@ -180,14 +182,14 @@
 #define CONFIG_NAND_FSL_ELBC           1
 
 #define CONFIG_SYS_NAND_BASE   0xE0600000
-#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\
+#define CONFIG_SYS_BR1_PRELIM  (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\
                                 BR_PS_8 | BR_MS_FCM | BR_V)
-#define CONFIG_SYS_OR1_PRELIM  (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\
                                 OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\
                                 OR_FCM_TRLX | OR_FCM_EHTR)
 
 #define CONFIG_SYS_LBLAWBAR1_PRELIM    CONFIG_SYS_NAND_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM     0x8000000E
+#define CONFIG_SYS_LBLAWAR1_PRELIM     (LBLAWAR_EN | LBLAWAR_32KB)
 
 /*
  * Serial Port
@@ -214,7 +216,6 @@
 
 /* Use the HUSH parser */
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 
 /* Pass open firmware flat tree */
 #define CONFIG_OF_LIBFDT       1
@@ -408,7 +409,7 @@
 /* DDR: cache cacheable */
 #define CONFIG_SYS_SDRAM       CONFIG_SYS_SDRAM_BASE
 
-#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT0L      (CONFIG_SYS_SDRAM | BATL_PP_RW |\
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT0U      (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\
                                 BATU_VP)
@@ -422,7 +423,7 @@
 #define CONFIG_SYS_DBAT1U      CONFIG_SYS_IBAT1U
 
 /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_IMMR | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT2L      (CONFIG_SYS_IMMR | BATL_PP_RW |\
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT2U      (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\
                                 BATU_VP)
@@ -436,23 +437,23 @@
 #define CONFIG_SYS_DBAT3U      CONFIG_SYS_IBAT3U
 
 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT4U      (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\
                                 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT4L      (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT4U      CONFIG_SYS_IBAT4U
 
 /* Stack in dcache: cacheable, no memory coherence */
-#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT5L      (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 #define CONFIG_SYS_IBAT5U      (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\
                                 BATU_VS | BATU_VP)
 #define CONFIG_SYS_DBAT5L      CONFIG_SYS_IBAT5L
 #define CONFIG_SYS_DBAT5U      CONFIG_SYS_IBAT5U
 
 /* PCI MEM space: cacheable */
-#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\
+#define CONFIG_SYS_IBAT6L      (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\
                                 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT6U      (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\
                                 BATU_VS | BATU_VP)
@@ -460,7 +461,7 @@
 #define CONFIG_SYS_DBAT6U      CONFIG_SYS_IBAT6U
 
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT7L      (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \
                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_IBAT7U      (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\
                                 BATU_VS | BATU_VP)