#ifdef CONFIG_FSLDMAFEC
# define CONFIG_NET_MULTI 1
# define CONFIG_MII 1
+# define CONFIG_MII_INIT 1
# define CONFIG_HAS_ETH1
+# define CFG_DMA_USE_INTSRAM 1
# define CFG_DISCOVER_PHY
# define CFG_RX_ETH_BUFFER 32
# define CFG_TX_ETH_BUFFER 48
# define CFG_FEC1_PINMUX 0
# define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
+# define MCFFEC_TOUT_LOOP 50000
/* If CFG_DISCOVER_PHY is not defined - hardcoded */
# ifndef CFG_DISCOVER_PHY
# define FECDUPLEX FULL
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCI 1
#define CONFIG_PCI_PNP 1
+#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
#define CFG_PCI_MEM_BUS 0x80000000
#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS
#define CFG_FLASH_CFI
#ifdef CFG_FLASH_CFI
# define CFG_FLASH_BASE (CFG_CS0_BASE)
-# define CFG_FLASH_CFI_DRIVER 1
+# define CONFIG_FLASH_CFI_DRIVER 1
# define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
# define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
# define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#define CFG_CS0_CTRL 0x00101980
#ifdef CFG_NOR1SZ
-#define CFG_CS1_BASE 0xF8000000
+#define CFG_CS1_BASE 0xE0000000
#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
-#define CFG_CS1_CTRL 0x00000D80
+#define CFG_CS1_CTRL 0x00101D80
#endif
#endif /* _M5485EVB_H */