Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE

[platform/kernel/u-boot.git] / include / configs / M5485EVB.h

diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index 28bf0ad..92fe316 100644 (file)
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -196,13 +196,13 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0xF2000000
-#define CONFIG_SYS_INIT_RAM_END        0x1000  /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE       0x1000  /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x21
-#define CONFIG_SYS_INIT_RAM1_ADDR      (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_END)
+#define CONFIG_SYS_INIT_RAM1_ADDR      (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
 #define CONFIG_SYS_INIT_RAM1_END       0x1000  /* End of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM1_CTRL      0x21
 #define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
@@ -266,13 +266,28 @@
 #define CONFIG_ENV_OFFSET              0x2000
 #define CONFIG_ENV_SECT_SIZE   0x2000
 #define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_IS_EMBEDDED 1
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_BCINVA + CF_CACR_ICINVA + \
+                                        CF_CACR_IDCM)
+#define CONFIG_SYS_DCACHE_INV          (CF_CACR_DCINVA)
+#define CONFIG_SYS_CACHE_ACR2          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_BEC | CF_CACR_BCINVA | \
+                                        CF_CACR_IEC | CF_CACR_ICINVA)
+#define CONFIG_SYS_CACHE_DCACR         ((CONFIG_SYS_CACHE_ICACR | \
+                                        CF_CACR_DEC | CF_CACR_DDCM_P | \
+                                        CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */