arch: m68k: Use existing CONFIG_MCFTMR instead of CFG_MCFTMR

[platform/kernel/u-boot.git] / include / configs / M5329EVB.h

diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h
index d7ece63..dd5d4c9 100644 (file)
--- a/include/configs/M5329EVB.h
+++ b/include/configs/M5329EVB.h
@@ -18,21 +18,11 @@
  * (easy to change)
  */
 
-#define CONFIG_SYS_UART_PORT           (0)
-
-#define CONFIG_WATCHDOG_TIMEOUT        5000    /* timeout in milliseconds, max timeout is 6.71sec */
+#define CFG_SYS_UART_PORT              (0)
 
 /* I2C */
 
-#ifdef CONFIG_MCFFEC
-#      define CONFIG_IPADDR    192.162.1.2
-#      define CONFIG_NETMASK   255.255.255.0
-#      define CONFIG_SERVERIP  192.162.1.1
-#      define CONFIG_GATEWAYIP 192.162.1.1
-#endif                         /* FEC_ENET */
-
-#define CONFIG_HOSTNAME                "M5329EVB"
-#define CONFIG_EXTRA_ENV_SETTINGS                                      \
+#define CFG_EXTRA_ENV_SETTINGS                                 \
        "netdev=eth0\0"                 \
        "loadaddr=40010000\0"   \
        "u-boot=u-boot.bin\0"   \
@@ -44,14 +34,14 @@
        "save\0"        \
        ""
 
-#define CONFIG_PRAM            512     /* 512 KB */
+#define CFG_PRAM               512     /* 512 KB */
 
-#define CONFIG_SYS_CLK                 80000000
-#define CONFIG_SYS_CPU_CLK             CONFIG_SYS_CLK * 3
+#define CFG_SYS_CLK                    80000000
+#define CFG_SYS_CPU_CLK                CFG_SYS_CLK * 3
 
-#define CONFIG_SYS_MBAR                0xFC000000
+#define CFG_SYS_MBAR           0xFC000000
 
-#define CONFIG_SYS_LATCH_ADDR          (CONFIG_SYS_CS1_BASE + 0x80000)
+#define CFG_SYS_LATCH_ADDR             (CFG_SYS_CS1_BASE + 0x80000)
 
 /*
  * Low Level Configuration Settings
@@ -61,9 +51,9 @@
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE       0x8000  /* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL       0x221
+#define CFG_SYS_INIT_RAM_ADDR  0x80000000
+#define CFG_SYS_INIT_RAM_SIZE  0x8000  /* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL  0x221
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
@@ -83,22 +73,22 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ           (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ              (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #ifdef CONFIG_SYS_FLASH_CFI
-#      define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
+#      define CFG_SYS_FLASH_SIZE               0x800000        /* Max size that the board might have */
 #endif
 
 #ifdef CONFIG_CMD_NAND
-#      define CFG_SYS_NAND_BASE                CONFIG_SYS_CS2_BASE
+#      define CFG_SYS_NAND_BASE                CFG_SYS_CS2_BASE
 #      define CFG_SYS_NAND_BASE_LIST   { CFG_SYS_NAND_BASE }
 #      define NAND_ALLOW_ERASE_ALL     1
 #endif
 
-#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE             CFG_SYS_CS0_BASE
 
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
@@ -112,15 +102,15 @@
  * Cache Configuration
  */
 
-#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
-                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
-#define CONFIG_SYS_CACHE_ACR0          (CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS                  (CFG_SYS_INIT_RAM_ADDR + \
+                                        CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CFG_SYS_INIT_RAM_ADDR + \
+                                        CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV             (CF_CACR_CINVA)
+#define CFG_SYS_CACHE_ACR0             (CFG_SYS_SDRAM_BASE | \
                                         CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
                                         CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+#define CFG_SYS_CACHE_ICACR            (CF_CACR_EC | CF_CACR_CINVA | \
                                         CF_CACR_DCM_P)
 
 /*-----------------------------------------------------------------------
@@ -134,18 +124,19 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE            0
-#define CONFIG_SYS_CS0_MASK            0x007f0001
-#define CONFIG_SYS_CS0_CTRL            0x00001fa0
+#define CFG_SYS_CS0_BASE               0
+#define CFG_SYS_CS0_MASK               0x007f0001
+#define CFG_SYS_CS0_CTRL               0x00001fa0
 
-#define CONFIG_SYS_CS1_BASE            0x10000000
-#define CONFIG_SYS_CS1_MASK            0x001f0001
-#define CONFIG_SYS_CS1_CTRL            0x002A3780
+#define CFG_SYS_CS1_BASE               0x10000000
+#define CFG_SYS_CS1_MASK               0x001f0001
+#define CFG_SYS_CS1_CTRL               0x002A3780
 
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_CS2_BASE            0x20000000
-#define CONFIG_SYS_CS2_MASK            (16 << 20)
-#define CONFIG_SYS_CS2_CTRL            0x00001f60
+#define CFG_SYS_CS2_BASE               0x20000000
+#define CFG_SYS_CS2_MASK               (16 << 20)
+#define CFG_SYS_CS2_CTRL               0x00001f60
 #endif
 
+
 #endif                         /* _M5329EVB_H */