i2c, soft-i2c: switch to new multibus/multiadapter support

[platform/kernel/u-boot.git] / include / configs / M53017EVB.h

diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index c351d41..bedba2b 100644 (file)
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -40,7 +40,6 @@
 #define CONFIG_MCFUART
 #define CONFIG_SYS_UART_PORT           (0)
 #define CONFIG_BAUDRATE                        115200
-#define CONFIG_SYS_BAUDRATE_TABLE      { 9600 , 19200 , 38400 , 57600, 115200 }
 
 #undef CONFIG_WATCHDOG
 #define CONFIG_WATCHDOG_TIMEOUT                5000
@@ -64,7 +63,6 @@
 
 #define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#      define CONFIG_NET_MULTI         1
 #      define CONFIG_MII               1
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
@@ -105,7 +103,6 @@
 /* I2C */
 #define CONFIG_FSL_I2C
 #define CONFIG_HARD_I2C                        /* I2C with hw support */
-#undef CONFIG_SOFT_I2C                 /* I2C bit-banged */
 #define CONFIG_SYS_I2C_SPEED           80000
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 #define CONFIG_SYS_I2C_OFFSET          0x58000
@@ -167,10 +164,9 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_END                0x20000 /* End of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_SIZE               0x20000 /* Size of used area in internal SRAM */
 #define CONFIG_SYS_INIT_RAM_CTRL       0x221
-#define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -233,6 +229,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+                                        CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */