Rename CONFIG_SYS_INIT_RAM_END into CONFIG_SYS_INIT_RAM_SIZE

[platform/kernel/u-boot.git] / include / configs / M53017EVB.h

diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h
index 801f90f..17efb63 100644 (file)
--- a/include/configs/M53017EVB.h
+++ b/include/configs/M53017EVB.h
@@ -69,6 +69,8 @@
 #      define CONFIG_MII_INIT          1
 #      define CONFIG_SYS_DISCOVER_PHY
 #      define CONFIG_SYS_RX_ETH_BUFFER 8
+#      define CONFIG_SYS_TX_ETH_BUFFER 8
+#      define CONFIG_SYS_FEC_BUF_USE_SRAM
 #      define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
 #      define CONFIG_HAS_ETH1
 
@@ -77,6 +79,9 @@
 #      define CONFIG_SYS_FEC1_PINMUX   0
 #      define CONFIG_SYS_FEC1_MIIBASE  CONFIG_SYS_FEC1_IOBASE
 #      define MCFFEC_TOUT_LOOP         50000
+
+#      define CONFIG_BOOTARGS          "root=/dev/mtdblock3 rw rootfstype=jffs2"
+
 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
 #      ifndef CONFIG_SYS_DISCOVER_PHY
 #              define FECDUPLEX        FULL
@@ -162,10 +167,10 @@
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x80000000
-#define CONFIG_SYS_INIT_RAM_END                0x20000 /* End of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL       0x21
+#define CONFIG_SYS_INIT_RAM_SIZE               0x20000 /* Size of used area in internal SRAM */
+#define CONFIG_SYS_INIT_RAM_CTRL       0x221
 #define CONFIG_SYS_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
+#define CONFIG_SYS_GBL_DATA_OFFSET     ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
 #define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -177,7 +182,7 @@
 #define CONFIG_SYS_SDRAM_SIZE          64      /* SDRAM size in MB */
 #define CONFIG_SYS_SDRAM_CFG1          0x43711630
 #define CONFIG_SYS_SDRAM_CFG2          0x56670000
-#define CONFIG_SYS_SDRAM_CTRL          0xE1002000
+#define CONFIG_SYS_SDRAM_CTRL          0xE1092000
 #define CONFIG_SYS_SDRAM_EMOD          0x80010000
 #define CONFIG_SYS_SDRAM_MODE          0x00CD0000
 
@@ -228,6 +233,17 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE      16
 
+#define ICACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS                  (CONFIG_SYS_INIT_RAM_ADDR + \
+                                        CONFIG_SYS_INIT_RAM_SIZE - 4)
+#define CONFIG_SYS_ICACHE_INV          (CF_CACR_CINVA)
+#define CONFIG_SYS_CACHE_ACR0          (CONFIG_SYS_SDRAM_BASE | \
+                                        CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+                                        CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR         (CF_CACR_EC | CF_CACR_CINVA | \
+                                        CF_CACR_DCM_P)
+
 /*-----------------------------------------------------------------------
  * Chipselect bank definitions
  */