+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Motorola MC5272C3 board.
*
* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/*
*/
#define CONFIG_MCFTMR
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
/* Configuration for environment
* Environment is embedded in u-boot in the second sector of the flash
*/
-#ifndef CONFIG_MONITOR_IS_IN_RAM
-#define CONFIG_ENV_OFFSET 0x4000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#else
-#define CONFIG_ENV_ADDR 0xffe04000
-#define CONFIG_ENV_SECT_SIZE 0x2000
-#endif
#define LDS_BOARD_TEXT \
. = DEFINED(env_offset) ? env_offset : .; \
env/embedded.o(.text);
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * Command line configuration.
- */
-
-#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
-# define CONFIG_MII 1
-# define CONFIG_MII_INIT 1
# define CONFIG_SYS_DISCOVER_PHY
-# define CONFIG_SYS_RX_ETH_BUFFER 8
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-
-# define CONFIG_SYS_FEC0_PINMUX 0
-# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
-# define MCFFEC_TOUT_LOOP 50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
# ifndef CONFIG_SYS_DISCOVER_PHY
# define FECDUPLEX FULL
# define FECSPEED _100BASET
-# else
-# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
-# endif
# endif /* CONFIG_SYS_DISCOVER_PHY */
#endif
"save\0" \
""
-#define CONFIG_SYS_LOAD_ADDR 0x20000
-#define CONFIG_SYS_MEMTEST_START 0x400
-#define CONFIG_SYS_MEMTEST_END 0x380000
#define CONFIG_SYS_CLK 66000000
/*
#endif
#define CONFIG_SYS_MONITOR_LEN 0x20000
-#define CONFIG_SYS_MALLOC_LEN (256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
/*
/*
* FLASH organization
*/
-#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
-# define CONFIG_FLASH_CFI_DRIVER 1
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
-# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
- * Memory bank definitions
- */
-#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
-#define CONFIG_SYS_BR1_PRELIM 0
-#define CONFIG_SYS_OR1_PRELIM 0
-#define CONFIG_SYS_BR2_PRELIM 0x30000001
-#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
-#define CONFIG_SYS_BR3_PRELIM 0
-#define CONFIG_SYS_OR3_PRELIM 0
-#define CONFIG_SYS_BR4_PRELIM 0
-#define CONFIG_SYS_OR4_PRELIM 0
-#define CONFIG_SYS_BR5_PRELIM 0
-#define CONFIG_SYS_OR5_PRELIM 0
-#define CONFIG_SYS_BR6_PRELIM 0
-#define CONFIG_SYS_OR6_PRELIM 0
-#define CONFIG_SYS_BR7_PRELIM 0x00000701
-#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
-
-/*-----------------------------------------------------------------------
* Port configuration
*/
#define CONFIG_SYS_PACNT 0x00000000