* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
-#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 5000
#ifdef CONFIG_MCFFEC
#define CONFIG_MCFTMR
/* I2C */
-#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
-
-#define CONFIG_UDP_CHECKSUM
#ifdef CONFIG_MCFFEC
# define CONFIG_IPADDR 192.162.1.2
#define CONFIG_PRAM 512 /* 512 KB */
-#define CONFIG_SYS_LOAD_ADDR 0x40010000
-
#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */
#define CONFIG_SYS_PLL_ODR 0x36
#define CONFIG_SYS_PLL_FDR 0x7D
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
/*
* For booting Linux, the board info and command line data
#ifdef CONFIG_SYS_FLASH_CFI
# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */
#endif
env/embedded.o(.text*);
/* Cache Configuration */
-#define CONFIG_SYS_CACHELINE_SIZE 16
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
CONFIG_SYS_INIT_RAM_SIZE - 8)