/*
- * (C) Copyright 2000-2004
+ * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
*
#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#endif
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
#define CONFIG_BOARD_TYPES 1 /* support board types */
#define CFG_8XX_FACT 8 /* Multiply by 8 */
#define CONFIG_EXTRA_ENV_SETTINGS \
"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
"run addhw;diskboot 200000 0:1;bootm 200000\0" \
-"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \
- "run addhw;diskboot 200000 2:1;bootm 200000\0" \
+"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
+ run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
+ usb stop; bootm 200000\0" \
"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
"panic_boot=echo No Bootdevice !!! reset\0" \
-"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
+"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
-"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):$(gatewayip)" \
- ":$(netmask):$(hostname):$(netdev):off\0" \
-"addhw=setenv bootargs $(bootargs) hw=$(hw) key1=$(key1) panic=1\0" \
+"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
+ ":${netmask}:${hostname}:${netdev}:off\0" \
+"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
"netdev=eth0\0" \
"silent=1\0" \
"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
-"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 $(filesize);" \
+"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
"cp.b 200000 40040000 14000\0"
#define CONFIG_BOOTCOMMAND \
- "run slot_a_boot;run nfs_boot;run panic_boot"
+ "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
#define CONFIG_MISC_INIT_R 1
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
-#undef CONFIG_WATCHDOG /* watchdog disabled */
+#define CONFIG_WATCHDOG 1 /* watchdog enabled */
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
-#define CONFIG_HARD_I2C
-#define CFG_I2C_SPEED 40000
-#define CFG_I2C_SLAVE 0x7F
+/*
+ * enable I2C and select the hardware/software driver
+ */
+#undef CONFIG_HARD_I2C /* I2C with hardware support */
+#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
+
+#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
+#define CFG_I2C_SLAVE 0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL 0x00000020 /* PB 26 */
+#define PB_SDA 0x00000010 /* PB 27 */
+
+#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
+#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
+#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
+ else immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+
+/*-----------------------------------------------------------------------
+ * I2C Configuration
+ */
+
+#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
+#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
+
-#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
+/* List of I2C addresses to be verified by POST */
+
+#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
+ CFG_I2C_RTC_ADDR, \
+ }
+
+
+#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
+
+#define CFG_DISCOVER_PHY
+#define CONFIG_MII
+
+#if 0
+#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
+#endif
#undef CONFIG_KUP4K_LOGO
/* Define to allow the user to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_I2C | \
- CFG_CMD_IDE )
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#if 1
+/* POST support */
+
+#define CONFIG_POST (CFG_POST_CPU | \
+ CFG_POST_RTC | \
+ CFG_POST_I2C)
+#endif
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_SNTP
+#define CONFIG_CMD_USB
+
+#ifdef CONFIG_POST
+ #define CONFIG_CMD_DIAG
+#endif
/*
* Miscellaneous configurable options
*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
#define CFG_ENV_IS_IN_FLASH 1
-#define CFG_ENV_OFFSET 0x30000 /* Offset of Environment Sector */
+#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
#define CFG_ENV_SECT_SIZE 0x10000
/*-----------------------------------------------------------------------
* Hardware Information Block
*/
-#if 0
-#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
-#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
-#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
+#if 1
+#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
+#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
+#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
#endif
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
*-----------------------------------------------------------------------
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
*/
-#if defined(CONFIG_WATCHDOG)
+#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
#define CONFIG_SILENT_CONSOLE 1
+#define CONFIG_USB_STORAGE 1
+#define CONFIG_USB_SL811HS 1
+
#endif /* __CONFIG_H */