rename CFG_ENV macros to CONFIG_ENV

[platform/kernel/u-boot.git] / include / configs / IVMS8.h

diff --git a/include/configs/IVMS8.h b/include/configs/IVMS8.h
index 2725e77..54477ee 100644 (file)
--- a/include/configs/IVMS8.h
+++ b/include/configs/IVMS8.h
@@ -72,24 +72,32 @@
 
 #define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
 
-#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | CFG_CMD_IDE)
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IDE
+
+
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
-#define CONFIG_BOOTP_MASK \
-    ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
 
-/*----------------------------------------------------------------------*/
 
 /*
  * Miscellaneous configurable options
  */
 #define        CFG_LONGHELP                    /* undef to save memory         */
 #define        CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 #else
 #define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
@@ -172,14 +180,14 @@
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
-#define        CFG_ENV_IS_IN_FLASH     1
-#define        CFG_ENV_OFFSET          0x7A000 /*   Offset   of Environment Sector     */
-#define        CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
+#define        CONFIG_ENV_IS_IN_FLASH  1
+#define        CONFIG_ENV_OFFSET               0x7A000 /*   Offset   of Environment Sector     */
+#define        CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value        */
 #endif
 
@@ -192,7 +200,7 @@
 #if defined(CONFIG_WATCHDOG)
 # if defined (CONFIG_IVMS8_16M)
 #   define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
-                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+                        SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #  elif defined (CONFIG_IVMS8_32M)
 #   define CFG_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
                         SYPCR_SWE  | SYPCR_SWP)
@@ -251,7 +259,7 @@
 /* 0x01800014 */
 #define CFG_SCCR       (SCCR_COM01     | /*SCCR_TBS|*/         \
                         SCCR_RTDIV     |   SCCR_RTSEL    |     \
-                        /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
+                        /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
                         SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
                         SCCR_DFBRG00   |   SCCR_DFNL000  |     \
                         SCCR_DFNH000   |   SCCR_DFLCD101 |     \
@@ -322,7 +330,6 @@
  *-----------------------------------------------------------------------
  *
  */
-/*#define      CFG_DER 0x2002000F*/
 #define CFG_DER        0
 
 /*
@@ -409,7 +416,7 @@
  */
 
 /* periodic timer for refresh */
-#define CFG_MAMR_PTB   204
+#define CFG_MBMR_PTB   204
 
 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit    */
 #define CFG_MPTPR_2BK_4K       MPTPR_PTP_DIV16         /* setting for 2 banks  */
@@ -432,19 +439,19 @@
 
 #if defined (CONFIG_IVMS8_16M)
  /* 8 column SDRAM */
-# define CFG_MBMR_8COL ((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-                        MAMR_AMB_TYPE_0 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A11 |   \
-                        MAMR_RLFB_1X    | MAMR_WLFB_1X    | MAMR_TLFB_4X)
+# define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+                        MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |   \
+                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_32M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL  ((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-                        MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |   \
-                        MAMR_RLFB_1X    | MAMR_WLFB_1X    | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+                        MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
+                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 #elif defined (CONFIG_IVMS8_64M)
 /* 128 MBit SDRAM */
-#define CFG_MBMR_8COL  ((CFG_MAMR_PTB << MAMR_PTB_SHIFT)  | \
-                        MAMR_AMB_TYPE_1 | MAMR_DSB_1_CYCL | MAMR_G0CLB_A10 |   \
-                        MAMR_RLFB_1X    | MAMR_WLFB_1X    | MAMR_TLFB_4X)
+#define CFG_MBMR_8COL  ((CFG_MBMR_PTB << MBMR_PTB_SHIFT)  | \
+                        MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |   \
+                        MBMR_RLFB_1X    | MBMR_WLFB_1X    | MBMR_TLFB_4X)
 
 #endif