* (easy to change)
*/
-#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
+#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_EXBITGEN 1 /* on a Exbit Generic board */
#define CFG_I2C_SLAVE 0x7F /* I2C slave address */
/* environment is in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM 1
+#define CONFIG_ENV_IS_IN_EEPROM 1
#undef CFG_ENV_IS_IN_FLASH
#undef CFG_ENV_IS_IN_NVRAM
-#ifdef CFG_ENV_IS_IN_EEPROM
+#ifdef CONFIG_ENV_IS_IN_EEPROM
#define CFG_I2C_EEPROM_ADDR 0x56 /* 1010110 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* 8-bit internal addressing */
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 1 /* ... and 1 bit in I2C address */
/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
* Command line configuration.
*/
#include <config_cmd_default.h>
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-/* Cache configuration */
-#define CFG_DCACHE_SIZE 8192
-#define CFG_CACHELINE_SIZE 32
-
/*
* Internal Definitions
*