* Scott McNutt <smcnutt@psyent.com>
* Stephan Linz <linz@li-pro.net>
*
+ * CompactFlash/IDE:
+ * (C) Copyright 2004, Shlomo Kut <skut@vyyo.com>
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
#ifndef __CONFIG_H
#define __CONFIG_H
-/*
- * NIOS CPU configuration.
+/***********************************************************************
+ * Include the whole NIOS CPU configuration.
*
- * Here we must define CPU dependencies. Any unsupported option have to
- * be defined with zero, example CPU without data cache / OCI:
+ * !!! HAVE TO BE HERE !!! DON'T MOVE THIS PART !!!
*
- * #define CFG_NIOS_CPU_ICACHE 4096
- * #define CFG_NIOS_CPU_DCACHE 0
- * #define CFG_NIOS_CPU_OCI_BASE 0
- * #define CFG_NIOS_CPU_OCI_SIZE 0
- */
+ ***********************************************************************/
#if defined(CONFIG_NIOS_SAFE_32)
-
-/* TODO */
-
+#include <configs/DK1C20_safe_32.h>
#elif defined(CONFIG_NIOS_STANDARD_32)
-
-/* CPU core */
-#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
-#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */
-#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */
-#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */
-#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */
-#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */
-#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
-#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
-#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */
-#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
- /* yes(1) */
-
-/* on-chip extensions */
-#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */
-#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */
-
-#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */
-#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
-
-#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */
-#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */
-
-/* timer */
-#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */
-
-#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */
-#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
-#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
-#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
- /* yes(1) */
-
-#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */
-#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */
-#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */
-#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */
- /* yes(1) */
-
-/* serial i/o */
-#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */
-
-#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */
-#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */
-#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
-#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
-#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
-#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
- /* odd(1) */
- /* even(2) */
-#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */
- /* crts(1) */
-#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
- /* yes(1) */
-
-/* parallel i/o */
-#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */
-
-#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */
-#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */
-#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */
-#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */
-#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */
-#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */
-#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */
-#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */
-#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */
-#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */
-#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
-#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */
-#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */
-#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
-#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */
-#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
-#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */
-#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */
-#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
-#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */
- /* out(1) */
- /* in(2) */
-#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */
- /* yes(1) */
-#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */
- /* fall(1) */
- /* rise(2) */
- /* any(3) */
-#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */
- /* level(1)*/
- /* edge(2) */
-
-/* IDE i/f */
-#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
-#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */
-
-/* active serial memory i/f */
-#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */
-#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */
-#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */
-
-/* memory accessibility */
-#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */
-#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */
-
-#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */
-#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
-
-#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */
-#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
-
-/* LAN */
-#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
-
-#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */
-#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */
-#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */
-#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/
-#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
- /* cs8900(1) */
- /* ex: alteramac(2) */
-
-/* symbolic redefinition (undef, if not present) */
-#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */
-#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/
-
-#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */
-#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */
-#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */
-#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */
-#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */
-#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */
-#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */
-#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */
-
+#include <configs/DK1C20_standard_32.h>
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif
#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
#define CFG_HZ 1000 /* 1 msec time tick */
#undef CFG_CLKS_IN_HZ
-#define CONFIG_BOARD_PRE_INIT 1 /* enable early board-spec. init*/
+#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
#if (CFG_NIOS_CPU_TICK_TIMER == 0)
-#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
+#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER0 /* TIMER0 as tick */
+#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER0_IRQ
+
+#if (CFG_NIOS_CPU_TIMER0_FP == 1) /* fixed period */
+
+#if (CFG_NIOS_CPU_TIMER0_PER >= CFG_HZ)
+#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER0_PER / CFG_HZ)
+#else
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
+
+#elif (CFG_NIOS_CPU_TIMER0_FP == 0) /* variable period */
+
+#if (CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER0_FP correct
+#endif
#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
+#if (CFG_NIOS_CPU_TIMER1_FP == 1) /* fixed period */
+
#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
-#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
+#error *** CFG_ERROR: you have to use a timer periode greater than CFG_HZ
+#endif
+
+#undef CFG_NIOS_TMRCNT /* no preloadable counter value */
+
+#elif (CFG_NIOS_CPU_TIMER1_FP == 0) /* variable period */
+
+#if (CFG_HZ <= 1000)
+#define CFG_NIOS_TMRMS (1000 / CFG_HZ)
+#else
+#error *** CFG_ERROR: sorry, CFG_HZ have to be less than 1000
+#endif
+
+#define CFG_NIOS_TMRCNT (CONFIG_SYS_CLK_FREQ / CFG_HZ)
+
+#else
+#error *** CFG_ERROR: you have to define CFG_NIOS_CPU_TIMER1_FP correct
#endif
#endif /* CFG_NIOS_CPU_TICK_TIMER */
#endif
/*------------------------------------------------------------------------
- * Ethernet -- needs work!
+ * Ethernet
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_LAN_NUMS == 1)
#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
- /****************************************************/
- /* !!! LAN91C111 works for NIOS with patch only !!! */
- /****************************************************/
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
-#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
-#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO1 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
-#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO2 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
-#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO4 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
-#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO5 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
-#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO6 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
-#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO7 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
-#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO8 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
-#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
+#error *** CFG_ERROR: seven segment display at PIO9 not supported, expand your config.h
#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
#endif /* CFG_NIOS_CPU_PIO_NUMS */
/*------------------------------------------------------------------------
- * COMMANDS
+ * ASMI - Active Serial Memory Interface.
+ *
+ * ASMI is for Cyclone devices only and only works when the configuration
+ * is loaded via JTAG or ASMI. Please see doc/README.dk1c20 for details.
*----------------------------------------------------------------------*/
-#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
- CFG_CMD_ASKENV | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_BMP | \
- CFG_CMD_BSP | \
- CFG_CMD_CACHE | \
- CFG_CMD_DATE | \
- CFG_CMD_DOC | \
- CFG_CMD_DTT | \
- CFG_CMD_EEPROM | \
- CFG_CMD_ELF | \
- CFG_CMD_FAT | \
- CFG_CMD_FDC | \
- CFG_CMD_FDOS | \
- CFG_CMD_HWFLOW | \
- CFG_CMD_IDE | \
- CFG_CMD_I2C | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_KGDB | \
- CFG_CMD_NAND | \
- CFG_CMD_MMC | \
- CFG_CMD_MII | \
- CFG_CMD_PCI | \
- CFG_CMD_PCMCIA | \
- CFG_CMD_SCSI | \
- CFG_CMD_SPI | \
- CFG_CMD_VFD | \
- CFG_CMD_USB ) )
-
-
-#include <cmd_confdefs.h>
+#define CONFIG_NIOS_ASMI /* Enable ASMI */
+#define CFG_NIOS_ASMIBASE CFG_NIOS_CPU_ASMI0 /* ASMI base address */
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_all.h>
+
+#undef CONFIG_CMD_ASKENV
+#undef CONFIG_CMD_BEDBUG
+#undef CONFIG_CMD_BMP
+#undef CONFIG_CMD_BSP
+#undef CONFIG_CMD_CACHE
+#undef CONFIG_CMD_DATE
+#undef CONFIG_CMD_DOC
+#undef CONFIG_CMD_DTT
+#undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_ELF
+#undef CONFIG_CMD_FDC
+#undef CONFIG_CMD_FDOS
+#undef CONFIG_CMD_HWFLOW
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_JFFS2
+#undef CONFIG_CMD_KGDB
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_MMC
+#undef CONFIG_CMD_MII
+#undef CONFIG_CMD_PCI
+#undef CONFIG_CMD_PCMCIA
+#undef CONFIG_CMD_REISER
+#undef CONFIG_CMD_SCSI
+#undef CONFIG_CMD_SPI
+#undef CONFIG_CMD_VFD
+#undef CONFIG_CMD_USB
+#undef CONFIG_CMD_XIMG
+
+
+/*------------------------------------------------------------------------
+ * COMPACT FLASH
+ *----------------------------------------------------------------------*/
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_IDE_PREINIT /* Implement id_preinit */
+#define CFG_IDE_MAXBUS 1 /* 1 IDE bus */
+#define CFG_IDE_MAXDEVICE 1 /* 1 drive per IDE bus */
+
+#define CFG_ATA_BASE_ADDR 0x00920a00 /* IDE/ATA base addr */
+#define CFG_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset */
+#define CFG_ATA_DATA_OFFSET 0x0040 /* Data IO offset */
+#define CFG_ATA_REG_OFFSET 0x0040 /* Register offset */
+#define CFG_ATA_ALT_OFFSET 0x0100 /* Alternate reg offset */
+#define CFG_ATA_STRIDE 4 /* Width betwix addrs */
+#define CONFIG_DOS_PARTITION
+
+/* Board-specific cf regs */
+#define CFG_CF_PRESENT 0x009209b0 /* CF Present PIO base */
+#define CFG_CF_POWER 0x009209c0 /* CF Power FET PIO base*/
+#define CFG_CF_ATASEL 0x009209d0 /* CF ATASEL PIO base */
+
+#endif
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
#undef CFG_MEMTEST_END
#endif
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV "nor0"
+#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
+#define CONFIG_JFFS2_PART_OFFSET 0x00000000
+
+/* mtdparts command line support */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT ""
+#define MTDPARTS_DEFAULT ""
+*/
#endif /* __CONFIG_H */
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