Makefile: move all Power Architecture boards into boards.cfg

[platform/kernel/u-boot.git] / include / configs / DB64360.h

diff --git a/include/configs/DB64360.h b/include/configs/DB64360.h
index daed934..3a20d02 100644 (file)
--- a/include/configs/DB64360.h
+++ b/include/configs/DB64360.h
@@ -120,6 +120,8 @@ if we use PCI it has its own MAC addr */
 
 #define CONFIG_DB64360         1       /* this is an DB64360 board     */
 
+#define        CONFIG_SYS_TEXT_BASE    0xfff00000
+
 #define CONFIG_BAUDRATE                115200  /* console baudrate = 115000    */
 /*ronen - we don't use the global CONFIG_ECC, since in the global ecc we initialize the
        DRAM for ECC in the phase we are relocating to it, which isn't so sufficient.
@@ -230,7 +232,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  *
  */
 /* No command line, one static partition, whole device */
-#undef CONFIG_JFFS2_CMDLINE
+#undef CONFIG_CMD_MTDPARTS
 #define CONFIG_JFFS2_DEV               "nor1"
 #define CONFIG_JFFS2_PART_SIZE         0xFFFFFFFF
 #define CONFIG_JFFS2_PART_OFFSET       0x00000000
@@ -242,7 +244,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
  * Note: fake mtd_id's used, no linux mtd map file.
  */
 /*
-#define CONFIG_JFFS2_CMDLINE
+#define CONFIG_CMD_MTDPARTS
 #define MTDIDS_DEFAULT         "nor1=db64360-1"
 #define MTDPARTS_DEFAULT       "mtdparts=db64360-1:-(jffs2)"
 */
@@ -318,8 +320,7 @@ ip=${ipaddr}:${serverip}${bootargs_end}; bootm 0x400000;\0"
 
 #define CONFIG_SYS_HZ                  1000            /* decr freq: 1ms ticks */
 /*ronen - this the Sys clock (cpu bus,internal dram and SDRAM) */
-#define CONFIG_SYS_BUS_HZ              133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
-#define CONFIG_SYS_BUS_CLK             CONFIG_SYS_BUS_HZ
+#define CONFIG_SYS_BUS_CLK             133000000       /* 133 MHz (CPU = 5*Bus = 666MHz)               */
 
 #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP 7 /* define the SDRAM cycle count */
 #define CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP 50 /* for 400MHZ -> 5.0 ns, for 133MHZ -> 7.50 ns */