/*
- * (C) Copyright 2001
+ * (C) Copyright 2001-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
#define CONFIG_CPU86 1 /* ...on a CPU86 board */
+#define CONFIG_CPM2 1 /* Has a CPM2 */
/*
* select serial console configuration
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
#define CONFIG_PREBOOT \
"echo; " \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"bootp; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
- "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
/*-----------------------------------------------------------------------
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
-#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
- CFG_CMD_BEDBUG | \
- CFG_CMD_EEPROM | \
- CFG_CMD_DATE | \
- CFG_CMD_I2C | \
- CFG_CMD_DOC)
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_BEDBUG | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_DOC | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_NFS | \
+ CFG_CMD_SNTP )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+#define CFG_NAND_LEGACY
+
/*
* Miscellaneous configurable options
*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
#define CFG_EEPROM_PAGE_WRITE_BITS 4
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_ENV_OFFSET 0
-#define CFG_ENV_SIZE 2048
+#define CFG_ENV_OFFSET 512
+#define CFG_ENV_SIZE (2048 - 512)
#endif
/*
* HID1 has only read-only information - nothing to set.
*/
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
- HID0_DCI|HID0_IFEM|HID0_ABE)
+ HID0_DCI|HID0_IFEM|HID0_ABE)
#define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE)
#define CFG_HID2 0
*/
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
+ SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
#else
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
+ SYPCR_SWRI|SYPCR_SWP)
#endif /* CONFIG_WATCHDOG */
/*-----------------------------------------------------------------------
/* Bank 0 - Boot ROM
*/
#define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
/* Bank 1 - FLASH
*/
#define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
#else /* CONFIG_BOOT_ROM */
/* Bank 0 - FLASH
*/
#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
/* Bank 1 - Boot ROM
*/
#define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_3_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_3_CLK |\
+ ORxU_EHTR_8IDLE)
#endif /* CONFIG_BOOT_ROM */
*/
#ifndef CFG_RAMBOOT
#define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_64 |\
- BRx_MS_SDRAM_P |\
- BRx_V)
+ BRx_PS_64 |\
+ BRx_MS_SDRAM_P |\
+ BRx_V)
#define CFG_OR2_PRELIM CFG_OR2_9COL
/* Bank 3 - Dual Ported SRAM
*/
#define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_SETA)
/* Bank 4 - DiskOnChip
*/
#define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_5_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_ACS_DIV2 |\
+ ORxG_SCY_5_CLK |\
+ ORxU_EHTR_8IDLE)
/* Bank 5 - FDC37C78 controller
*/
#define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\
- ORxG_ACS_DIV2 |\
- ORxG_SCY_8_CLK |\
- ORxU_EHTR_8IDLE)
+ ORxG_ACS_DIV2 |\
+ ORxG_SCY_8_CLK |\
+ ORxU_EHTR_8IDLE)
/* Bank 6 - Board control registers
*/
#define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\
- BRx_PS_8 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_8 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\
- ORxG_CSNT |\
- ORxG_SCY_5_CLK)
+ ORxG_CSNT |\
+ ORxG_SCY_5_CLK)
/* Bank 7 - VME Extended Access Range
*/
#define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\
- BRx_PS_32 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_32 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_SETA)
/* Bank 8 - VME Standard Access Range
*/
#define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_SETA)
/* Bank 9 - VME Short I/O Access Range
*/
#define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\
- BRx_PS_16 |\
- BRx_MS_GPCM_P |\
- BRx_V)
+ BRx_PS_16 |\
+ BRx_MS_GPCM_P |\
+ BRx_V)
#define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\
- ORxG_CSNT |\
- ORxG_ACS_DIV1 |\
- ORxG_SCY_5_CLK |\
- ORxG_SETA)
+ ORxG_CSNT |\
+ ORxG_ACS_DIV1 |\
+ ORxG_SCY_5_CLK |\
+ ORxG_SETA)
#endif /* __CONFIG_H */
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