#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
-#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
- CONFIG_BOOTP_DNS | \
- CONFIG_BOOTP_DNS2 | \
- CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_DHCP | \
- CFG_CMD_PCI | \
- CFG_CMD_IRQ | \
- CFG_CMD_IDE | \
- CFG_CMD_FAT | \
- CFG_CMD_ELF | \
- CFG_CMD_DATE | \
- CFG_CMD_JFFS2 | \
- CFG_CMD_I2C | \
- CFG_CMD_MII | \
- CFG_CMD_PING | \
- CFG_CMD_BSP | \
- CFG_CMD_EEPROM )
-
-#if 0 /* test-only */
-#define CONFIG_NETCONSOLE
-#define CONFIG_NET_MULTI
-
-#ifdef CONFIG_NET_MULTI
-#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */
-#endif
-#endif
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_EEPROM
#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION
#undef CONFIG_AUTO_UPDATE /* autoupdate via compactflash */
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
#define CFG_PROMPT_HUSH_PS2 "> "
#endif
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
/* Only interrupt boot if special string is typed */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds\n"
+#define CONFIG_AUTOBOOT_KEYED 1
+#define CONFIG_AUTOBOOT_PROMPT \
+ "Autobooting in %d seconds\n", bootdelay
#undef CONFIG_AUTOBOOT_DELAY_STR
#undef CONFIG_AUTOBOOT_STOP_STR /* defined via environment var */
#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd" /* esd special for esd access*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-
#if 0 /* Use NVRAM for environment variables */
/*-----------------------------------------------------------------------
* NVRAM organization
*/
-#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
-#define CFG_ENV_ADDR \
- (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CFG_ENV_SIZE+8)) /* Env */
+#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
+#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
+#define CONFIG_ENV_ADDR \
+ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-(CONFIG_ENV_SIZE+8)) /* Env */
#else /* Use EEPROM for environment variables */
-#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
+#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
/* total size of a CAT24WC16 is 2048 bytes */
#endif
/* 16 byte page write mode using*/
/* last 4 bits of the address */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CFG_EEPROM_PAGE_WRITE_ENABLE
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */
- /* have only 8kB, 16kB is save here */
-#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Init Memory Controller:
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
-
/*
* Internal Definitions
*
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