include/configs/[A-G]*: Directly use CONFIG_BOOTP_* symbols rather than CONFIG_BOOTP_...
[platform/kernel/u-boot.git] / include / configs / CPCI405AB.h
index aaaafa9..1aefbba 100644 (file)
 #define CONFIG_MII             1       /* MII PHY management           */
 #define CONFIG_PHY_ADDR                0       /* PHY address                  */
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NET_MULTI       1
+#undef  CONFIG_HAS_ETH1
 
 #define CONFIG_RTC_M48T35A     1               /* ST Electronics M48 timekeeper */
 
-#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
-                                CONFIG_BOOTP_DNS | \
-                                CONFIG_BOOTP_DNS2 | \
-                                CONFIG_BOOTP_SEND_HOSTNAME )
-
-#define CONFIG_COMMANDS              ( CONFIG_CMD_DFL  | \
-                               CFG_CMD_DHCP    | \
-                               CFG_CMD_PCI     | \
-                               CFG_CMD_IRQ     | \
-                               CFG_CMD_IDE     | \
-                               CFG_CMD_FAT     | \
-                               CFG_CMD_ELF     | \
-                               CFG_CMD_DATE    | \
-                               CFG_CMD_JFFS2   | \
-                               CFG_CMD_I2C     | \
-                               CFG_CMD_MII     | \
-                               CFG_CMD_PING    | \
-                               CFG_CMD_EEPROM  )
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_EEPROM
+
 
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_SUPPORT_VFAT
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
+#define CFG_NAND_LEGACY
+
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
 #define CFG_PROMPT_HUSH_PS2    "> "
 #endif
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE     1024            /* Console I/O Buffer Size      */
 #else
 #define CFG_CBSIZE     256             /* Console I/O Buffer Size      */
 #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405      */
 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A   */
 #define CFG_PCI_CLASSCODE      0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000      /* point to sdram               */
-#define CFG_PCI_PTM1MS 0xfc000001      /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
+#define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 #define CFG_PCI_PTM1PCI 0x00000000     /* Host: use this pci address   */
 #define CFG_PCI_PTM2LA 0xffc00000      /* point to flash               */
 #define CFG_PCI_PTM2MS 0xffc00001      /* 4MB, enable                  */
 #define CFG_DCACHE_SIZE                16384   /* For AMCC 405 CPUs, older 405 ppc's   */
                                        /* have only 8kB, 16kB is save here     */
 #define CFG_CACHELINE_SIZE     32      /* ...                  */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 #endif