ppc4xx: Big header cleanup part 2, mostly PPC405 related

[platform/kernel/u-boot.git] / include / configs / CMS700.h

diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 40fef88..ede9970 100644 (file)
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -80,8 +80,6 @@
 
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_I2C
@@ -167,31 +165,6 @@
 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 #define CONFIG_SYS_NAND_QUIET          1
 
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0             /* configure as pci adapter     */
-#define PCI_HOST_FORCE 1               /* configure as pci host        */
-#define PCI_HOST_AUTO  2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI                     /* include pci support          */
-#define CONFIG_PCI_HOST PCI_HOST_HOST  /* select pci host function     */
-#undef CONFIG_PCI_PNP                  /* do pci plug-and-play         */
-                                       /* resource configuration       */
-
-#undef CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
-#define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
-#define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
-#define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -222,21 +195,16 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains U-Boot */
-#endif
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE          0x00000000
-#define CONFIG_SYS_FLASH_BASE          0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE        TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
-#define CONFIG_SYS_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
+#define CONFIG_SYS_FLASH_BASE          CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE                TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN         (~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN          (256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT            1
@@ -256,6 +224,7 @@
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C                        /* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C              /* use PPC4xx driver            */
 #define CONFIG_SYS_I2C_SPEED           100000  /* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE           0x7F
 
@@ -291,8 +260,7 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL         1           /* using Xilinx XC95XL CPLD      */
-#define CONFIG_SYS_FPGA_MAX_SIZE       32*1024     /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR   0xfffc0000
 
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG            0x04000000  /* JTAG TMS pin (ppc output)     */
@@ -333,12 +301,12 @@
 /* GPIO Output:                OSR=00, ISR=00, TSR=00, TCR=1 */
 /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */
 /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */
-#define CONFIG_SYS_GPIO0_OSRH          0x40000500  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_OSRL          0x00000110  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_ISR1H         0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_ISR1L         0x14000045  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /*  0 ... 15 */
-#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_OSRL          0x40000500  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_OSRH          0x00000110  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_ISR1L         0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_ISR1H         0x14000045  /* 16 ... 31 */
+#define CONFIG_SYS_GPIO0_TSRL          0x00000000  /*  0 ... 15 */
+#define CONFIG_SYS_GPIO0_TSRH          0x00000000  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TCR           0xF7FE0014  /*  0 ... 31 */
 
 #define CONFIG_SYS_EEPROM_WP           (0x80000000 >> 8)    /* GPIO8 */
@@ -356,17 +324,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
-#define PLLMR0_DEFAULT  PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT  PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT  PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT  PLLMR1_200_100_50_33
-#endif
-#if 1
 #define PLLMR0_DEFAULT  PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT  PLLMR1_133_66_66_33
-#endif
 
 #endif /* __CONFIG_H */